公开(公告)号：US11899532B2

公开(公告)日：2024-02-13

申请号：US17804826

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Giuseppe Cariello ,  Jameer Mulani

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0757 ,  G06F11/0772

Abstract: Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.

公开(公告)号：US20230176778A1

公开(公告)日：2023-06-08

申请号：US17457829

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jotiba Koparde

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0667 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

公开(公告)号：US20240345743A1

公开(公告)日：2024-10-17

申请号：US18603033

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Nitul Gohain ,  Amiya Banerjee ,  Rakeshkumar Dayabhai Vaghasiya

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive polling for higher density storage are described. A controller of a memory system may identify a temperature of the memory device and select one or more polling parameters that are associated with identifying a status of the memory device based on a temperature of a memory system. In some cases, the controller may perform a polling operation according to the one or more polling parameters based on selecting the one or more polling parameters.

公开(公告)号：US20240289236A1

公开(公告)日：2024-08-29

申请号：US18581275

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jonathan S. Parry

IPC: G06F11/14

CPC classification number: G06F11/1469

Abstract: Methods, systems, and devices for efficient data management for memory system error handling are described. If a new data transfer is desired between the controller and a memory device when the latches are full, the controller may obtain data that has been loaded in one of the latches, temporarily store that data in a buffer, and overwrite the latch with the new data associated with the new data transfer. After the controller is finished working with the new data now stored in the latch, the controller may restore the data from the buffer to the latch so the prior data transfer may continue. This may prevent loss of data or reduce the quantity of data that is temporarily lost from latches and needs to be re-transferred when the latches are full.

公开(公告)号：US20240192890A1

公开(公告)日：2024-06-13

申请号：US18513310

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Amiya Banerjee ,  Nitul Gohain

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

公开(公告)号：US20240069776A1

公开(公告)日：2024-02-29

申请号：US18237737

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Hong Lu ,  Kulachet Tanpairoj ,  Chun Sum Yeung ,  Jameer Mulani ,  Nitul Gohain ,  Uday Bhasker V. Vudugandla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

公开(公告)号：US20240045762A1

公开(公告)日：2024-02-08

申请号：US17883051

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jonathan S. Parry ,  Reshmi Basu

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.

公开(公告)号：US12061819B2

公开(公告)日：2024-08-13

申请号：US17457829

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jotiba Koparde

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0667 ,  G06F3/0673

Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.

公开(公告)号：US20240232011A1

公开(公告)日：2024-07-11

申请号：US18397889

申请日：2023-12-27

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Amiya Banerjee ,  Nitul Gohain

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F13/1673

Abstract: Methods, systems, and devices for techniques for improved data transfer are described. As part of a data transfer operation from a first set of memory cells of a memory device to a second set of memory cells of the memory device, a memory controller of may read a set of data units from the first set of memory cells. The memory device 240 may transmit the set of data units to the memory controller. The memory controller may decode the set of data units, and, in some cases, may generate one or more corrected data units. The memory controller may then generate parity information for the set of data units, and may encode and write the parity information, along with any corrected data units, to the second set of memory cells of the memory device without transferring the uncorrected data units.

公开(公告)号：US20240220144A1

公开(公告)日：2024-07-04

申请号：US18534363

申请日：2023-12-08

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/0292

Abstract: Methods, systems, and devices for techniques for concurrent host system access and data folding are described. A memory system may determine to transfer (e.g., fold) data from a set of source data blocks to a set of destination data blocks. The memory system may receive a command to access a first source data block of the set of source data blocks concurrent with the data transfer. The memory system may generate a first order for transferring respective portions of the data that is based on a second order associated with a sequential read of the data from the set of destination data blocks. Based on the accessing the first source data block being concurrent with the data transfer, the first order may exclude a first portion of the data from the first source data block such that the data transfer and the accessing may be concurrently performed.