公开(公告)号：US09558831B2

公开(公告)日：2017-01-31

申请号：US14715169

申请日：2015-05-18

Applicant: Micron Technology, Inc.

Inventor： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。

公开(公告)号：US09263130B2

公开(公告)日：2016-02-16

申请号：US14324969

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Paul D. Ruby ,  Violante Moschiano

IPC: G11C16/10 ,  G11C14/00 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C14/0018 ,  G11C16/0483 ,  G11C16/3427

Abstract: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

Abstract translation: 描述了包括存储器阵列中的页缓冲器之间的通信电路的存储器件和方法。 示例包括提供与给定页面缓冲器直接相邻的页面缓冲器的状态信息的通信电路。 交换的信息可以用于调整给定的页面缓冲器以补偿在同时操作的直接相邻数据线中的效果。

公开(公告)号：US20140321205A1

公开(公告)日：2014-10-30

申请号：US14324969

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Paul D. Ruby ,  Violante Moschiano

IPC: G11C14/00 ,  G11C16/04

CPC classification number: G11C14/0018 ,  G11C16/0483 ,  G11C16/3427

Abstract: Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

Abstract translation: 描述了包括存储器阵列中的页缓冲器之间的通信电路的存储器件和方法。 示例包括提供与给定页面缓冲器直接相邻的页面缓冲器的状态信息的通信电路。 交换的信息可以用于调整给定的页面缓冲器以补偿在同时操作的直接相邻数据线中的效果。

公开(公告)号：US09996496B2

公开(公告)日：2018-06-12

申请号：US15685855

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Doyle Rivers ,  Paul D. Ruby ,  Anand S. Ramalingam ,  Rajesh Sundaram ,  Julie M. Walker

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4247 ,  G06F13/14 ,  G06F13/385

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

公开(公告)号：US09477616B2

公开(公告)日：2016-10-25

申请号：US13961377

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Doyle Rivers ,  Paul D. Ruby ,  Anand S. Ramalingam ,  Rajesh Sundaram ,  Julie M. Walker

IPC: G06F13/14

CPC classification number: G06F13/4247 ,  G06F13/14 ,  G06F13/385

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract translation: 描述了芯片选择的几种系统和方法。 在一种这样的方法中，设备维护两个标识符（ID_a和ID_m）。 当设备接收到命令时，它检查ID_a和ID_m相对于第三参考标识符（ID_s）的值。 如果ID_a或ID_m等于ID_s，则设备执行该命令，否则设备将忽略该命令。 通过使用两种不同的识别方法，系统具有选择激活设备的选项，能够以快速方式选择多个设备和单个设备之间进行选择性切换。 在另一种这样的方法中，设备可以具有存储诸如ID_a的标识信息的持久区域。 因此，系统功能可以独立于与系统中所有设备的初始ID_a分配所需的物理或逻辑组件相关联的任何缺陷/边际。

公开(公告)号：US20150248937A1

公开(公告)日：2015-09-03

申请号：US14715169

申请日：2015-05-18

Applicant: Micron Technology, Inc.

Inventor： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。

公开(公告)号：US08638612B2

公开(公告)日：2014-01-28

申请号：US13854549

申请日：2013-04-01

Applicant: Micron Technology, Inc.

Inventor： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

IPC: G11C11/34

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

Abstract translation: 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。