Devices, systems, and methods of reducing chip select

    公开(公告)号:US10289597B2

    公开(公告)日:2019-05-14

    申请号:US15975637

    申请日:2018-05-09

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

    公开(公告)号:US20180329854A1

    公开(公告)日:2018-11-15

    申请号:US15975637

    申请日:2018-05-09

    CPC classification number: G06F13/4247 G06F13/14 G06F13/385

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

    公开(公告)号:US20160328353A1

    公开(公告)日:2016-11-10

    申请号:US15212902

    申请日:2016-07-18

    CPC classification number: G06F13/4247 G06F13/14 G06F13/385

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    NON-VOLATILE MEMORY PROGRAMMING
    4.
    发明申请

    公开(公告)号:US20130286743A1

    公开(公告)日:2013-10-31

    申请号:US13925192

    申请日:2013-06-24

    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

    公开(公告)号:US20170351637A1

    公开(公告)日:2017-12-07

    申请号:US15685855

    申请日:2017-08-24

    CPC classification number: G06F13/4247 G06F13/14 G06F13/385

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    Non-volatile memory programming
    6.
    发明授权
    Non-volatile memory programming 有权
    非易失性存储器编程

    公开(公告)号:US09042184B2

    公开(公告)日:2015-05-26

    申请号:US13925192

    申请日:2013-06-24

    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

    Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后,以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。

    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
    7.
    发明申请
    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT 有权
    设备,系统和减少芯片选择的方法

    公开(公告)号:US20150046611A1

    公开(公告)日:2015-02-12

    申请号:US13961377

    申请日:2013-08-07

    CPC classification number: G06F13/4247 G06F13/14 G06F13/385

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    Abstract translation: 描述了芯片选择的几种系统和方法。 在一种这样的方法中,设备维护两个标识符(ID_a和ID_m)。 当设备接收到命令时,它检查ID_a和ID_m相对于第三参考标识符(ID_s)的值。 如果ID_a或ID_m等于ID_s,则设备执行该命令,否则设备将忽略该命令。 通过使用两种不同的识别方法,系统具有选择激活设备的选项,能够以快速方式选择多个设备和单个设备之间进行选择性切换。 在另一种这样的方法中,设备可以具有存储诸如ID_a的标识信息的持久区域。 因此,系统功能可以独立于与系统中所有设备的初始ID_a分配所需的物理或逻辑组件相关联的任何缺陷/边际。

    Non-volatile memory apparatus and methods
    8.
    发明授权
    Non-volatile memory apparatus and methods 有权
    非易失性存储装置及方法

    公开(公告)号:US08767472B2

    公开(公告)日:2014-07-01

    申请号:US13862999

    申请日:2013-04-15

    Inventor: Paul D. Ruby

    CPC classification number: G11C16/10 G11C16/0483 G11C16/26 G11C16/34

    Abstract: Some embodiments include apparatus and methods having memory cells coupled in series and a module to cause an application of voltages with at least three different values to gates of the memory cells during an operation to retrieve information stored in at least one of the memory cells. Additional apparatus and methods are described.

    Abstract translation: 一些实施例包括具有串联耦合的存储器单元的装置和方法以及在操作期间使存储单元的栅极具有至少三个不同值的电压的应用以检索存储在至少一个存储单元中的信息的模块。 描述附加的装置和方法。

    AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE
    9.
    发明申请
    AUTOMATIC SELECTIVE SLOW PROGRAM CONVERGENCE 有权
    自动选择性缓慢计划的融合

    公开(公告)号:US20130215680A1

    公开(公告)日:2013-08-22

    申请号:US13854549

    申请日:2013-04-01

    Abstract: Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

    Abstract translation: 公开了装置,方法和系统,包括使用自动选择性慢程序融合(ASSPC)来提高编程电压分配宽度的装置,方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压(Vt)是否已经达到特定的预编程验证电压。 响应于该确定,施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加,直到单元被适当地编程为止。 还描述了另外的实施例。

    Devices, systems, and methods of reducing chip select

    公开(公告)号:US09785603B2

    公开(公告)日:2017-10-10

    申请号:US15212902

    申请日:2016-07-18

    CPC classification number: G06F13/4247 G06F13/14 G06F13/385

    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

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