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    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    11.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20230113573A1

    公开(公告)日：2023-04-13

    申请号：US18048633

    申请日：2022-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

    ELECTRON BEAM PROBING TECHNIQUES AND RELATED STRUCTURES
    13.
    发明申请
    ELECTRON BEAM PROBING TECHNIQUES AND RELATED STRUCTURES 有权

    公开(公告)号：US20220301946A1

    公开(公告)日：2022-09-22

    申请号：US17714770

    申请日：2022-04-06

    Applicant: Micron Technology, Inc.

    Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

    IPC: H01L21/66 ,  H01L21/768 ,  H01L27/24 ,  H01J37/28 ,  H01L23/528

    Abstract: Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

    SOCKET DESIGN FOR A MEMORY DEVICE
    14.
    发明申请
    SOCKET DESIGN FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210151105A1

    公开(公告)日：2021-05-20

    申请号：US16685349

    申请日：2019-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

    IPC: G11C13/00 ,  H01L23/528 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00

    Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES
    17.
    发明公开
    STRUCTURES AND METHODS FOR DICING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230290684A1

    公开(公告)日：2023-09-14

    申请号：US17690981

    申请日：2022-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Wei Chang Wong ,  Radhakrishna Kotti ,  Raj K. Bansal ,  Youngik Kwon ,  Po Chih Yang ,  Venkateswarlu Bhavanasi

    IPC: H01L21/78 ,  H01L23/58

    CPC classification number: H01L21/78 ,  H01L23/585 ,  H01L27/108

    Abstract: Structures and methods for separating semiconductor wafers into individual dies are disclosed. A semiconductor wafer or panel can include a crack assist structure in a scribe junction. The crack assist structure can include a plurality of vertical walls extending at least partially through a thickness of the wafer. In some embodiments, the plurality of vertical walls can be coupled to a weak interface. The weak interface can guide cracks that form during the dicing process in a direction along the walls, away from active circuitry. After dicing, the resulting semiconductor devices can include a plurality of vertical walls extending at least partially through a thickness of the semiconductor device. Each of the plurality of vertical walls can include at least a portion extending substantially parallel to a sidewall of the semiconductor device.

    Methods for forming conductive vias, and associated devices and systems
    18.
    发明授权
    Methods for forming conductive vias, and associated devices and systems 有权

    公开(公告)号：US11515204B2

    公开(公告)日：2022-11-29

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    19.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20220336277A1

    公开(公告)日：2022-10-20

    申请号：US17230833

    申请日：2021-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

    IPC: H01L21/768 ,  H01L23/535

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    20.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20220208606A1

    公开(公告)日：2022-06-30

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

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