公开(公告)号：US12058853B2

公开(公告)日：2024-08-06

申请号：US17115469

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Surendranath C. Eruvuru

IPC: H10B41/27 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/823437 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/092 ,  H10B43/27

Abstract: An electronic device includes one or more capacitors adjacent to a base material. The one or more capacitors comprise at least one electrode extending horizontally within the base material, and additional electrodes extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US20240250024A1

公开(公告)日：2024-07-25

申请号：US18420074

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Surendranath C. Eruvuru ,  Lifang Xu

IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A stairless electrical interconnect structure with contact pillars embedded within and collectively accessing each tier in a periodic material stack, e.g., to provide electrical connections to access lines associated with a three-dimensional memory array, is described. The contact pillars can be formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages to create depths of the trenches that vary between columns by a fixed number of tiers and then offset the depths between rows.

公开(公告)号：US20240055350A1

公开(公告)日：2024-02-15

申请号：US17819538

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Mark S. Swenson ,  Surendranath C. Eruvuru ,  Lifang Xu

IPC: H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/53295 ,  H01L21/76837

Abstract: An electronic device comprises a stack comprising an alternating sequence of conductive structures and insulative structures arranged in tiers, and at least one dielectric-filled slot extending vertically through the stack and extending in a first horizontal direction. The at least one dielectric-filled slot is defined between two internal sidewalls of the stack. The electronic device comprises additional dielectric-filled slots extending vertically through the stack and extending in a second horizontal direction transverse to the first horizontal direction, and isolation structures laterally interposed between the at least one dielectric-filled slot and the additional dielectric-filled slots. The isolation structures are laterally adjacent to the conductive structures of the stack, and at least some of the isolation structures are vertically adjacent to the insulative structures of the stack. Related systems and methods of forming the electronic devices are also disclosed.

公开(公告)号：US20230047662A1

公开(公告)日：2023-02-16

申请号：US17445045

申请日：2021-08-13

Applicant: Micron Technology, Inc.

Inventor： Erwin E. Yu ,  Michele Piccardi ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02 ,  H01L23/538 ,  H01L27/092

Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.

公开(公告)号：US20220189874A1

公开(公告)日：2022-06-16

申请号：US17121645

申请日：2020-12-14

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Surendranath C. Eruvuru

IPC: H01L23/528 ,  H01L23/522

Abstract: Semiconductor devices with slotted vias, and associated systems and methods, are disclosed herein. In one embodiment, a routing region of the semiconductor device includes a set of slotted vias arranged in a non-orthogonal array pattern. Further, patterns of metal lines associated with the set of slotted vias are drawn to align and/or overlap with the slotted vias. As a result, the metal lines may include zig-zag patterns within the routing region. Further, edges of the slotted vias may have a staircase pattern with sets of horizontal and vertical line segments such that a combination of the horizontal and vertical line segments can orient the slotted vias in a non-orthogonal direction.