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    Memory Arrays and Methods of Forming Memory Arrays
    12.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 审中-公开

    公开(公告)号：US20180138238A1

    公开(公告)日：2018-05-17

    申请号：US15854534

    申请日：2017-12-26

    Applicant: Micron Technology, Inc.

    Inventor： Tony M. Lindenberg

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.

    Chemical mechanical planarization topography control via implant
    13.
    发明授权
    Chemical mechanical planarization topography control via implant 有权
    通过植入物进行化学机械平面化地形控制

    公开(公告)号：US09401285B2

    公开(公告)日：2016-07-26

    申请号：US14571946

    申请日：2014-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Andrew Carswell ,  Tony M. Lindenberg ,  Mark Morley ,  Kyle Ritter ,  Lequn Liu

    IPC: H01L21/306 ,  H01L29/36 ,  H01L21/02 ,  H01L21/308 ,  H01L29/16 ,  H01L23/528

    CPC classification number: H01L21/02532 ,  H01L21/02694 ,  H01L21/31053 ,  H01L21/31155 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Systems and methods for chemical mechanical planarization topography control via implants are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes increasing the content of at least one of silicon or germanium in at least select regions of a dielectric material thereby reducing the material removal rate for a chemical mechanical polishing (CMP) process at the select regions, and removing material from the dielectric material using the CMP process. In another embodiment, a method of manufacturing a semiconductor device includes increasing content of at least one of boron, phosphorus, or hydrogen in at least select regions of a dielectric material thereby increasing the material removal rate of a CMP process at the select regions, and removing material from the dielectric material using the CMP process.

    Abstract translation: 公开了通过植入物进行化学机械平面化地形控制的系统和方法。 在一个实施例中，制造半导体器件的方法包括增加介电材料的至少选择区域中的硅或锗中的至少一种的含量，从而降低在选择时的化学机械抛光（CMP）工艺的材料去除速率 区域，并且使用CMP工艺从电介质材料中去除材料。 在另一个实施例中，制造半导体器件的方法包括在介电材料的至少选择区域中增加硼，磷或氢中的至少一种的含量，从而增加在选择区域的CMP工艺的材料去除速率，以及 使用CMP工艺从电介质材料中去除材料。

    Array of cross point memory cells and methods of forming an array of cross point memory cells
    14.
    发明授权
    Array of cross point memory cells and methods of forming an array of cross point memory cells 有权
    交叉点存储单元阵列和形成交叉点存储单元阵列的方法

    公开(公告)号：US09362494B2

    公开(公告)日：2016-06-07

    申请号：US14293577

    申请日：2014-06-02

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2472 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

    Abstract translation: 交叉点存储单元的阵列包括间隔开的内部第一线，与第一线交叉的间隔开的外部第二直线，以及在第一和第二线之间的高阻状态区域，这样的交叉。 多电阻状态区域的个体包括彼此电耦合的高度外部的多重电阻状态材料和正向内部多电阻状态材料。 内部多阻态材料具有垂直横截面中的相对边缘。 外部多阻态材料在垂直横截面中具有相对于内部多阻态材料的相对边缘在垂直横截面中横向偏移的相对边缘。 还公开了方法。

    Inductive testing probe apparatus for testing semiconductor die and related systems and methods
    16.
    发明授权
    Inductive testing probe apparatus for testing semiconductor die and related systems and methods 有权

    公开(公告)号：US10852344B2

    公开(公告)日：2020-12-01

    申请号：US15839559

    申请日：2017-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Tony M. Lindenberg ,  Kurt J. Bossart ,  Jonathan S. Hacker ,  Chandra S. Tiwari

    IPC: G01R31/28 ,  H01L21/67 ,  G01R1/073 ,  H01L21/68

    Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

    INDUCTIVE TESTING PROBE APPARATUS FOR TESTING SEMICONDUCTOR DIE AND RELATED SYSTEMS AND METHODS
    17.
    发明申请
    INDUCTIVE TESTING PROBE APPARATUS FOR TESTING SEMICONDUCTOR DIE AND RELATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190178933A1

    公开(公告)日：2019-06-13

    申请号：US15839559

    申请日：2017-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Tony M. Lindenberg ,  Kurt J. Bossart ,  Jonathan S. Hacker ,  Chandra S. Tiwari

    IPC: G01R31/28 ,  H01L21/67 ,  H01L21/68 ,  G01R1/073

    Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

    Memory Arrays
    18.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20150279906A1

    公开(公告)日：2015-10-01

    申请号：US14242588

    申请日：2014-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Tony M. Lindenberg

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675

    Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.

    Abstract translation: 一些实施例包括存储器阵列，其具有沿着第一方向延伸的第一系列的存取/检测线，以及在第一系列存取/感测线上方的第二系列的存取/感测线，并且沿第二方向延伸，该第二方向穿过第一方向 方向。 存储单元垂直地位于第一和第二系列访问/感测线之间。 每个存储单元通过来自第一系列的访问/感测线和来自第二系列的访问/感测线的组合唯一地寻址。 电阻增加材料与第一和第二系列之一的访问/感测线相邻并且共同延伸，并且在相邻的存取/感测线和存储器单元的可编程材料之间。 一些实施例包括形成存储器阵列的方法。

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