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    Fuse array layout pattern and related apparatuses, systems, and methods
    11.
    发明授权
    Fuse array layout pattern and related apparatuses, systems, and methods 有权

    公开(公告)号：US11942167B2

    公开(公告)日：2024-03-26

    申请号：US16799011

    申请日：2020-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Jing Wang ,  Zhiwei Liang ,  Raghu Sreeramaneni

    IPC: G11C17/18 ,  G11C17/16 ,  H10B20/20

    CPC classification number: G11C17/16 ,  G11C17/18 ,  H10B20/20

    Abstract: Systems, methods, and apparatuses relating to interlocking transistor active regions are disclosed. An apparatus includes a gate including electrically conductive material and an active material including a doped semiconductor material. A portion of the active material overlapped by the gate has an at least substantially triangular shape. An apparatus includes a plurality of active materials. Each active material includes tapered ends and a plurality of gates. The plurality of active materials is arranged in an interlocking pattern with at least some tapered ends of the active materials interlocking with at least some others of the tapered ends. The plurality of gates overlaps the interlocked tapered ends of the plurality of active materials.

    STARTUP PROTECTION FOR STANDBY AMPLIFIERS
    13.
    发明申请
    STARTUP PROTECTION FOR STANDBY AMPLIFIERS 有权

    公开(公告)号：US20230140202A1

    公开(公告)日：2023-05-04

    申请号：US17514785

    申请日：2021-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Mishal Kumar ,  Wei Lu Chu

    IPC: H03K17/10 ,  H03K17/687 ,  H03K17/732 ,  H03K17/30 ,  G11C5/14

    Abstract: Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.

    Memory system capable of compensating for kickback noise
    14.
    发明授权
    Memory system capable of compensating for kickback noise 有权

    公开(公告)号：US11450373B2

    公开(公告)日：2022-09-20

    申请号：US17003163

    申请日：2020-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Dong Pan

    IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4091 ,  H03H7/06 ,  G11C7/14 ,  G05F1/575 ,  G11C11/4063

    Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.

    AMPLIFIER WITH A CONTROLLABLE PULL-DOWN CAPABILITY FOR A MEMORY DEVICE
    15.
    发明申请
    AMPLIFIER WITH A CONTROLLABLE PULL-DOWN CAPABILITY FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220200538A1

    公开(公告)日：2022-06-23

    申请号：US17127172

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Zhi Qi Huang ,  Dong Pan

    IPC: H03F1/30 ,  H03F1/02 ,  G11C7/06

    Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.

    Voltage drop mitigation techniques for memory devices
    16.
    发明授权
    Voltage drop mitigation techniques for memory devices 有权

    公开(公告)号：US11315627B1

    公开(公告)日：2022-04-26

    申请号：US16950593

    申请日：2020-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Wei Lu Chu ,  Dong Pan

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4063 ,  G11C11/22 ,  G11C11/408

    Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.

    METHODS AND APPARATUSES INCLUDING A PROCESS, VOLTAGE, AND TEMPERATURE INDEPENDENT CURRENT GENERATOR CIRCUIT
    18.
    发明申请
    METHODS AND APPARATUSES INCLUDING A PROCESS, VOLTAGE, AND TEMPERATURE INDEPENDENT CURRENT GENERATOR CIRCUIT 审中-公开

    公开(公告)号：US20190171246A1

    公开(公告)日：2019-06-06

    申请号：US16273528

    申请日：2019-02-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Wei Lu Chu

    IPC: G05F3/30 ,  G11C5/14

    Abstract: Apparatuses, methods, and current generators that generate current are described. An example apparatus includes a current source configured to provide a current. The current source may be coupled to a voltage source via a transistor. The transistor may be configured to provide the voltage source to the current source based on a voltage of a gate of the transistor. The example apparatus may further include an amplifier configured to provide a voltage to the gate of the transistor based on a voltage differential between two inputs. The voltage differential between the two inputs may adjust due to process, voltage or temperature changes such that the current provided by the current source remains constant.

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