公开(公告)号：US11227869B1

公开(公告)日：2022-01-18

申请号：US17111746

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C5/06 ,  G11C5/02 ,  G11C16/34 ,  H01L27/11582

Abstract: Arrays of memory cells a plurality of sense lines each having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of unit column structures capacitively coupled to first channels of its respective plurality of pass gates, wherein, for each sense line of the plurality of sense lines, each unit column structure of its respective subset of unit column structures is connected to a respective first data line of a respective subset of first data lines.

公开(公告)号：US20220013450A1

公开(公告)日：2022-01-13

申请号：US16924506

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US20250046381A1

公开(公告)日：2025-02-06

申请号：US18924115

申请日：2024-10-23

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

Abstract: A memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is coupled to the SA latch and coupled to sense node. Control logic is coupled to the SA latch and the DL. The control logic causes a pre-program verify voltage to boost the sense node. In response to detecting a high bit value stored in SA latch, the control logic causes a voltage to turn on set transistor(s) of the DL so that a first bias voltage or a second bias voltage is stored at a latch transistor.

公开(公告)号：US12080356B2

公开(公告)日：2024-09-03

申请号：US17876718

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

公开(公告)号：US11678482B2

公开(公告)日：2023-06-13

申请号：US17557389

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  G11C16/34 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  G11C5/025 ,  G11C5/06 ,  G11C16/3427 ,  H01L27/11582

Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

公开(公告)号：US11562799B2

公开(公告)日：2023-01-24

申请号：US17463645

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: Memory devices might include an array of memory cells including a plurality of strings of series-connected memory cells, a plurality of access lines, a common source, a plurality of data lines, a plurality of shield lines, and control logic. Each access line might be connected to a control gate of a respective memory cell of each string of series-connected memory cells. Each string of series-connected memory cells might be selectively connected between the common source and a respective data line. The plurality of shield lines might be interleaved with the plurality of data lines. The control logic might be configured to implement a program verify operation of respective memory cells coupled to a selected access line including sensing a voltage level on each data line to determine whether each respective memory cell coupled to the selected access line has been programmed to a target level for the respective memory cell.

公开(公告)号：US20220383960A1

公开(公告)日：2022-12-01

申请号：US17876718

申请日：2022-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: Methods of forming integrated circuit structures for a capacitive sense NAND memory include forming a first semiconductor overlying a dielectric, forming a second semiconductor to be in contact with a first end of the first semiconductor, forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor, forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor, and forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.

公开(公告)号：US20220336490A1

公开(公告)日：2022-10-20

申请号：US17811037

申请日：2022-07-06

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Yoshihiko Kamata ,  Yoshiaki Fukuzumi ,  Tamotsu Murakoshi

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/24 ,  H01L27/02 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573

Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11437106B2

公开(公告)日：2022-09-06

申请号：US17111729

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C11/04 ,  G11C16/26 ,  G11C16/04

Abstract: An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.

公开(公告)号：US20220180939A1

公开(公告)日：2022-06-09

申请号：US17111770

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10

Abstract: Memory might include a non-volatile memory cell, a capacitance selectively connected to the non-volatile memory cell, a field-effect transistor having a channel capacitively coupled to an electrode of the capacitance, and a controller for access of the non-volatile memory cell configured to cause the memory to increase a voltage level of the electrode of the capacitance, selectively discharge the voltage level of the electrode of the capacitance through the non-volatile memory cell responsive to a data state stored in the non-volatile memory cell, and determine whether the field-effect transistor is activated in response to a remaining voltage level of the electrode of the capacitance.