公开(公告)号：US6144075A

公开(公告)日：2000-11-07

申请号：US177787

申请日：1998-10-22

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/092 ,  H01L29/76

CPC分类号： H01L27/0928

摘要： An inverter formed in a semiconductor substrate is disclosed. The inverter comprises: a p-well formed in the substrate, the p-well being the output of the inverter; a gate structure formed atop the p-well, the gate structure being the input of the inverter and being formed from a thin gate oxide layer underneath a conductive layer; an n- base formed adjacent to a first edge of the gate structure; a p+ structure formed within the n- base; and a n+ structure adjacent a second edge of the gate structure.

摘要翻译： 公开了一种形成在半导体衬底中的逆变器。 逆变器包括：在衬底中形成的p阱，p阱是逆变器的输出; 栅极结构形成在p阱的顶部，栅极结构是反相器的输入，并由导电层下面的薄栅氧化层形成; 形成在栅极结构的第一边缘附近的n基底; 在n基中形成的p +结构; 以及与栅极结构的第二边缘相邻的n +结构。

公开(公告)号：US6143607A

公开(公告)日：2000-11-07

申请号：US411133

申请日：1999-10-01

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L29/861 ,  H01L21/336

CPC分类号： H01L29/8616 ,  H01L21/28273 ,  H01L29/7885

摘要： A method of forming an ETOX-cell in a semiconductor substrate is disclosed. The method begins with forming a p-well in the substrate. Then, a drain region and a source region is formed in the p-well. The drain region is of a first dopant type and the source region is of a second dopant type (i.e. same as the dopant type of the p-well). A floating-gate and tunnel oxide stack is formed above the p-well, the floating gate formed between the drain region and the source region and only after the drain region and the source region have been formed. The floating gate is doped with the same dopant type as the p-well. Finally, a control gate is formed above the floating-gate, the floating-gate and the control gate separated by a dielectric layer. The new ETOX cells can be organized into a NOR array, but with no need of source line connections. Each cell is programmed by band-to-band induced substrate hot-electron (BBISHE) at the source, and read by GIDL at the drain side.

摘要翻译： 公开了一种在半导体衬底中形成ETOX电池的方法。 该方法开始于在衬底中形成p阱。 然后，在p阱中形成漏极区域和源极区域。 漏极区域是第一掺杂剂类型，并且源极区域是第二掺杂剂型（即，与p阱的掺杂剂类型相同）。 在p阱的上方形成浮置栅极和隧道氧化物堆叠，形成在漏极区域和源极区域之间并且仅在形成漏极区域和源极区域之后的浮置栅极。 浮栅掺杂与p阱相同的掺杂剂类型。 最后，在浮置栅极，浮栅和控制栅极之上形成控制栅极，由栅介质层分隔开。 新的ETOX单元可以组织成NOR阵列，但不需要源线连接。 每个单元由源极处的带 - 带诱导衬底热电子（BBISHE）编程，并在漏极侧由GIDL读取。

公开(公告)号：US6091635A

公开(公告)日：2000-07-18

申请号：US275523

申请日：1999-03-24

申请人： Min-hwa Chi ,  Chih Ming Chen

发明人： Min-hwa Chi ,  Chih Ming Chen

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  G11C16/00

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/10

摘要： A new method for injecting electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a p-well formed in the n-well, a drain implant formed in the p-well, and a source implant formed in the p-well. The method comprises the steps of: forward biasing the deep n-well relative to the p-well; positively biasing the control gate by a voltage sufficient to invert the channel between the source implant and the drain implant; and positively biasing the source and drain. The SHE programming has at least 100 times higher efficiency than channel hot electron (CHE). The cell threshold voltage (V.sub.T) saturates to a value in a self-convergent manner. The SHE can also be used for tightening the Vt spread by a re-programming technique after erase.

摘要翻译： 一种用于在衬底热电子（SHE）编程期间将电子从正向偏压深n阱注入到三阱ETOX电池的沟道区域下方的p阱结的新方法。 ETOX单元具有控制栅极，浮置栅极，在衬底中形成的深n阱，在n阱中形成的p阱，形成在p阱中的漏极注入，以及形成在p阱中的源极注入 p井。 该方法包括以下步骤：相对于p阱向前偏置深n阱; 使控制栅极正向偏置足以反转源极注入和漏极注入之间的沟道的电压; 并积极偏置源极和漏极。 SHE编程具有比通道热电子（CHE）高至少100倍的效率。 电池阈值电压（VT）以自会聚的方式饱和到一个值。 擦除后，SHE也可用于通过重新编程技术来紧固Vt扩展。

公开(公告)号：US5856222A

公开(公告)日：1999-01-05

申请号：US851252

申请日：1997-05-05

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM cell access transistor and the EEPROM cell storage cell structure, respectively.

摘要翻译： 在半导体衬底中制造EEPROM单元结构的方法包括在硅衬底上形成具有第一厚度的氧化硅层。 然后将N型掺杂剂引入半导体衬底中以限定氧化硅层下面的掩埋区域。 接下来，在氧化硅层中形成隧道窗口以露出掩埋区域的表面区域。 然后在掩埋区域的暴露表面上的隧道窗口中生长隧道氧化物层，使得隧道氧化物的厚度小于氧化硅的厚度。 然后在由上述步骤产生的结构上形成第一层多晶硅，随后是氧化物+ 544氮化物+ 544氧化物（ONO）的覆盖层和第二多晶硅的上覆层。 然后各向异性地蚀刻poly-2，ONO + 544 poly-1夹层以形成分别为EEPROM单元存取晶体管和EEPROM单元存储单元结构提供浮置栅极/控制栅电极的第一和第二堆叠。

公开(公告)号：US5761126A

公开(公告)日：1998-06-02

申请号：US796616

申请日：1997-02-07

申请人： Min-hwa Chi ,  Chih Sieh Teng ,  Albert Bergemont

发明人： Min-hwa Chi ,  Chih Sieh Teng ,  Albert Bergemont

IPC分类号： G11C16/04 ,  H01L29/788 ,  G11C11/34

CPC分类号： G11C16/0408 ,  H01L29/7881 ,  G11C2216/10

摘要： The layout and the programming voltage of a single-poly EPROM cell are reduced by eliminating the n+ contact region which is conventionally utilized to place a positive voltage on the n-well of the cell, and by utilizing a negative voltage to program the cell. The negative voltage is applied to a p+ contact region formed in the n-well which injects electrons directly onto the floating gate of the cell.

摘要翻译： 通过消除通常用于在电池的n阱上放置正电压的n +接触区域，并且通过利用负电压来对电池进行编程来减小单聚EPROM单元的布局和编程电压。 负电压被施加到形成在n阱中的p +接触区域，其将电子直接注入到电池的浮动栅极上。

公开(公告)号：US5587949A

公开(公告)日：1996-12-24

申请号：US429644

申请日：1995-04-27

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C13/00

CPC分类号： G11C16/10 ,  G11C11/5621 ,  G11C11/5628

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an ETOX array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

摘要翻译： 通过将相应数量的编程电压中的一个应用于与要编程的单元相对应的字线，可以将多个逻辑电平同时编程到ETOX阵列列中的存储单元的任何组合。 在本发明中，阵列中的存储单元在编程期间形成穿透电流，这又导致形成更多数量的衬底热电子。 除了沟道热电子之外，通过利用由穿通电流形成的衬底热电子，在编程期间可以利用更低的控制栅极电压。

公开(公告)号：US5557567A

公开(公告)日：1996-09-17

申请号：US417938

申请日：1995-04-06

申请人： Albert Bergemont ,  Min-hwa Chi

发明人： Albert Bergemont ,  Min-hwa Chi

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0491 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5622

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an alternate-metal virtual-ground (AMG) EPROM or flash memory array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

摘要翻译： 可以将多个逻辑电平同时编程到备用金属虚拟地（AMG）EPROM或闪存阵列的列中的存储器单元的任意组合中，通过将相应数量的编程电压中的一个应用于与 要编程的单元格。 在本发明中，阵列中的存储单元在编程期间形成穿透电流，这又导致形成更多数量的衬底热电子。 除了沟道热电子之外，通过利用由穿通电流形成的衬底热电子，在编程期间可以利用更低的控制栅极电压。

公开(公告)号：US07002213B2

公开(公告)日：2006-02-21

申请号：US10642416

申请日：2003-08-15

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L27/01

CPC分类号： H01L29/7841 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78612

摘要： A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the VCC and VSS. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.

摘要翻译： 公开了在薄SOI上制造的晶体管结构。 薄SOI上的晶体管具有门控n +和p +结，其用作在结的表面上接通和关断GIDL电流的开关。 GIDL电流将流入浮体并钳位其电位，因此可用作输出节点。 晶体管可以作为逆变器。 物体（n阱或p阱）与n +或P +“GIDL开关”隔离相反掺杂类型的区域，即p基极和n基极。 诸如NAND和NOR门之类的逻辑电路的基本构成块可以用薄SOI晶片上的这种晶体管容易地实现。 薄SOI上的这些新晶体管仅需要V CC和V SS上的触点和金属线路连接。 扇出（输出和输入之间）的连接可以通过电容耦合实现。 晶体管结构和操作对SOI晶圆上的高性能，低电压和低功耗VLSI电路是有用的。

公开(公告)号：US06905929B1

公开(公告)日：2005-06-14

申请号：US10281763

申请日：2002-10-28

申请人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  G11C2216/10 ,  H01L27/115

摘要： Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design. This is permitted because the VTp implant step is masked, permitting the control gate region to operate in accumulation mode during application of 5V programming voltages.

摘要翻译： 通过消除从控制栅极n阱分离源极，沟道和漏极的场氧化物，并且通过用重掺杂的表面隔离区域代替围绕电池的场氧化物来防止单聚EPROM单元的泄漏。 EPROM单元还利用在控制栅极区域上具有开放矩形浮动栅极部分的浮动栅极，以及在沟道上方的窄浮动栅极部分和中间的硅衬底。 开放式矩形浮动栅极部分的表面积确保与控制栅极区域的高耦合率。 窄浮动栅极部分的小宽度防止在n阱和源极，沟道和漏极之间形成相当大的泄漏路径。 为了节省表面积，EPROM单元还消除了常规EPROM设计中控制栅极中的p +接触区域和PLDD区域。 这是允许的，因为V FET注入步骤被屏蔽，允许控制栅极区域在施加5V编程电压期间以累积模式工作。

公开(公告)号：US06281550B1

公开(公告)日：2001-08-28

申请号：US09286946

申请日：1999-04-08

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  Y10S438/91

摘要： A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the Vcc and Vss. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for highperformance, low-voltage, and low-power VLSI circuits on SOI wafers.

摘要翻译： 公开了在薄SOI上制造的晶体管结构。 薄SOI上的晶体管具有门控n +和p +结，其用作在结的表面上接通和关断GIDL电流的开关。 GIDL电流将流入浮体并钳位其电位，因此可用作输出节点。 晶体管可以作为逆变器。 物体（n阱或p阱）与n +或P +“GIDL开关”隔离相反掺杂类型的区域，即p基极和n基极。 诸如NAND和NOR门之类的逻辑电路的基本构成块可以用薄SOI晶片上的这种晶体管容易地实现。 薄SOI上的这些新晶体管只需要Vcc和Vss上的触点和金属线连接。 扇出（输出和输入之间）的连接可以通过电容耦合实现。 晶体管结构和操作对于SOI晶片上的高性能，低电压和低功率VLSI电路是有用的。