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    Current-controlled oscillator (CCO) based PLL
    11.
    发明授权
    Current-controlled oscillator (CCO) based PLL 有权
    基于电流控制振荡器（CCO）的PLL

    公开(公告)号：US08432204B1

    公开(公告)日：2013-04-30

    申请号：US13344637

    申请日：2012-01-06

    申请人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei ,  Fu-Lung Hsueh

    IPC分类号： H03L7/06

    CPC分类号： H03L7/102 ,  H03L7/099 ,  H03L7/104

    摘要： A PLL circuit includes a phase frequency detector; a programmable charge pump coupled to an output of the phase frequency detector; a loop filter coupled to an output of the charge pump, the loop filter providing a fine tuning voltage; a first voltage-to-current converter, the first voltage-to-current converter providing a fine tuning current corresponding to the fine tuning voltage; a current-controlled oscillator (CCO); a feedback divider coupled to an output of the CCO and an input of the phase frequency detector; and an analog calibration circuit. The analog calibration circuit provides a coarse adjustment current for coarse adjustments to a frequency pivot point for an oscillator frequency of the CCO, wherein the CCO generates a frequency signal at an output responsive to a summed coarse adjustment and fine tuning current, wherein the frequency pivot point is continuously adjustable.

    摘要翻译： PLL电路包括相位检波器; 耦合到所述相位频率检测器的输出的可编程电荷泵; 耦合到电荷泵的输出的环路滤波器，所述环路滤波器提供微调电压; 第一电压 - 电流转换器，第一电压 - 电流转换器提供对应于微调电压的微调电流; 电流控制振荡器（CCO）; 耦合到CCO的输出的反馈分压器和相位频率检测器的输入端; 和模拟校准电路。 模拟校准电路提供用于对CCO的振荡器频率的频率枢转点进行粗调整的粗调电流，其中CCO响应于总和的粗调和微调电流而在输出端产生频率信号，其中频率枢轴 点连续可调。

    Method of operating voltage regulator
    13.
    发明授权
    Method of operating voltage regulator 有权
    操作电压调节器的方法

    公开(公告)号：US08766613B2

    公开(公告)日：2014-07-01

    申请号：US13744037

    申请日：2013-01-17

    申请人： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    发明人： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    IPC分类号： G05F1/44

    CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

    摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

    摘要翻译： 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

    Voltage regulator with high accuracy and high power supply rejection ratio
    15.
    发明授权
    Voltage regulator with high accuracy and high power supply rejection ratio 有权
    电压调节器具有高精度和高电源抑制比

    公开(公告)号：US08378654B2

    公开(公告)日：2013-02-19

    申请号：US12750260

    申请日：2010-03-30

    申请人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    发明人： Chan-Hong Chern ,  Tzu Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    IPC分类号： G05F1/44

    CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

    摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

    摘要翻译： 提供了具有高精度和电源抑制比（PSRR）的稳压电路。 在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。 电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。 运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。 运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。 运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。 在另一个实施例中，PMOS和NMOS晶体管的作用相反。

    Charge pump doubler
    17.
    发明授权
    Charge pump doubler 有权
    电荷泵倍增器

    公开(公告)号：US08324960B2

    公开(公告)日：2012-12-04

    申请号：US12849503

    申请日：2010-08-03

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： H02M3/07

    摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

    摘要翻译： 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

    Voltage regulators, memory circuits, and operating methods thereof
    18.
    发明授权
    Voltage regulators, memory circuits, and operating methods thereof 有权
    电压调节器，存储器电路及其操作方法

    公开(公告)号：US09489989B2

    公开(公告)日：2016-11-08

    申请号：US12820712

    申请日：2010-06-22

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C7/06 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

    摘要翻译： 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

    Level shifters having diode-connected devices for input-output interfaces
    19.
    发明授权
    Level shifters having diode-connected devices for input-output interfaces 有权
    电平移位器具有用于输入 - 输出接口的二极管连接器件

    公开(公告)号：US08436671B2

    公开(公告)日：2013-05-07

    申请号：US12859456

    申请日：2010-08-19

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Chih-Chang Lin ,  Yuwen Swei ,  Ming-Chieh Huang

    IPC分类号： H03L5/00

    CPC分类号： H03K3/02 ,  H03K19/018521 ,  H03K19/018528

    摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.

    摘要翻译： 电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。 电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。 高电源电压高于第一电压电平。 所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。 第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

    VOL up-shifting level shifters
    20.
    发明授权
    VOL up-shifting level shifters 有权
    VOL上移电平转换器

    公开(公告)号：US08207775B2

    公开(公告)日：2012-06-26

    申请号：US12871343

    申请日：2010-08-30

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

    摘要： A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

    摘要翻译： 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。