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25 条记录 (耗时 0.057 秒)

    Charge pump doubler
    2.
    发明授权
    Charge pump doubler 有权
    电荷泵倍增器

    公开(公告)号：US08324960B2

    公开(公告)日：2012-12-04

    申请号：US12849503

    申请日：2010-08-03

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Yuwen Swei

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： H02M3/07

    摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.

    摘要翻译： 集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。 第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。 集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

    Voltage regulators, memory circuits, and operating methods thereof
    3.
    发明授权
    Voltage regulators, memory circuits, and operating methods thereof 有权
    电压调节器，存储器电路及其操作方法

    公开(公告)号：US09489989B2

    公开(公告)日：2016-11-08

    申请号：US12820712

    申请日：2010-06-22

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tien Chun Yang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C7/06 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

    摘要翻译： 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

    Method and apparatus for feedback-based resistance calibration
    4.
    发明授权
    Method and apparatus for feedback-based resistance calibration 有权
    用于基于反馈的电阻校准的方法和装置

    公开(公告)号：US09134360B2

    公开(公告)日：2015-09-15

    申请号：US13547101

    申请日：2012-07-12

    申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： H03L5/00 ,  G01R31/26

    CPC分类号： G01R31/2621

    摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

    摘要翻译： 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

    Drivers having T-coil structures
    5.
    发明授权
    Drivers having T-coil structures 有权
    驱动器具有T型线圈结构

    公开(公告)号：US08896352B2

    公开(公告)日：2014-11-25

    申请号：US13278742

    申请日：2011-10-21

    申请人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

    发明人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

    IPC分类号： H03K3/00

    CPC分类号： H03H11/44 ,  H01S5/0427 ,  H04B10/504

    摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

    摘要翻译： 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

    Phase interpolator for clock data recovery circuit with active wave shaping integrators
    6.
    发明授权
    Phase interpolator for clock data recovery circuit with active wave shaping integrators 有权
    具有有源波形整形器的时钟数据恢复电路的相位内插器

    公开(公告)号：US08873689B2

    公开(公告)日：2014-10-28

    申请号：US13564758

    申请日：2012-08-02

    申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： H04L7/00

    CPC分类号： H03K5/135 ,  H03H11/20 ,  H03K2005/00052 ,  H04L7/0029

    摘要： A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

    摘要翻译： 用于CDR电路的相位插值器产生具有在两个输入时钟上的电平转换之间的电平转换的输出时钟。 输入时钟驱动交叉耦合差分放大器，输出可根据输入控制值通过可变电流节流或转向相位变化。 差分放大器产生一个输出信号，该输出信号跨越在引导输入时钟之间的转换开始到延迟输入时钟转换结束之间的时间。 输出时钟是线性的，只要两个输入时钟的转换重叠即可。 每个具有串联电阻和电容反馈路径的放大器的积分器耦合到交叉耦合差分放大器的每个输入，这增强了输入时钟上升时间的重叠，并提高了内插输出信号的线性度。

    Decision feedback equalizer
    8.
    发明授权
    Decision feedback equalizer 有权
    决策反馈均衡器

    公开(公告)号：US08862951B2

    公开(公告)日：2014-10-14

    申请号：US13528877

    申请日：2012-06-21

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    IPC分类号： G06F11/00 ,  H04L27/01

    CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

    摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

    摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。

    Method of operating voltage regulator
    10.
    发明授权
    Method of operating voltage regulator 有权
    操作电压调节器的方法

    公开(公告)号：US08766613B2

    公开(公告)日：2014-07-01

    申请号：US13744037

    申请日：2013-01-17

    申请人： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    发明人： Chan-Hong Chern ,  Tzu-Ching Chang ,  Min-Shueh Yuan ,  Yuwen Swei ,  Chih-Chang Lin ,  Chiang Pu ,  Ming-Chieh Huang ,  Kuoyuan Hsu

    IPC分类号： G05F1/44

    CPC分类号： H02M3/158 ,  G05F1/44 ,  G05F1/56

    摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

    摘要翻译： 一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。 控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。 通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。 响应于输出节点处的电压电平产生反馈信号。 耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。