公开(公告)号：US5960455A

公开(公告)日：1999-09-28

申请号：US777038

申请日：1996-12-30

申请人： Mitchell A. Bauman

发明人： Mitchell A. Bauman

IPC分类号： G06F12/08

CPC分类号： G06F12/0811

摘要： Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

摘要翻译： 一种计算机系统的方法和装置，用于在对称的多处理环境中有效地操作多个指令处理器和输入/输出子系统。 计算机系统使用具有高性能互连方案的新的存储控制器，其增加了附加的公共存储控制器模块来扩展系统性能。 互连方案具有总线连接系统的成本优势，同时实现了交叉连接系统的性能特征。

公开(公告)号：US20130132061A1

公开(公告)日：2013-05-23

申请号：US13299458

申请日：2011-11-18

申请人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn ,  Nathan Zimmer

发明人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn ,  Nathan Zimmer

IPC分类号： G06F9/455

CPC分类号： G06F9/45554 ,  G06F2009/45583

摘要： A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit. The computing system includes a linker configured to manage association of at least one of the one or more translated memory banks to the interface layer for native execution by the programmable circuit in place of a corresponding bank of non-native instructions.

摘要翻译： 一种用于执行软件程序的计算系统和方法以及用于仿真计算环境的指令的翻译。 计算系统包括能够执行第一指令集架构的本机指令并且不能执行第二指令集架构的非本地指令的可编程电路。 仿真器在接口层内运行，并且转换托管在仿真操作系统中的非本机应用程序以供执行。 计算系统包括至少部分由仿真的操作系统定义的翻译的存储器组，并且能够在可编程电路上进行本地执行，其中仿真操作系统不能在可编程电路上执行。 计算系统包括链接器，其被配置为管理一个或多个翻译的存储器组中的至少一个与接口层的关联，用于由可编程电路代替相应的非本机指令组进行本地执行。

公开(公告)号：US07213109B1

公开(公告)日：2007-05-01

申请号：US10304919

申请日：2002-11-26

申请人： Mitchell A. Bauman ,  Joseph S. Schibinger

发明人： Mitchell A. Bauman ,  Joseph S. Schibinger

IPC分类号： G06F13/00 ,  G06F12/00 ,  G06F3/00 ,  G06F13/18

CPC分类号： G06F12/0817 ,  G06F2212/507

摘要： A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

摘要翻译： 提供了一种用于管理存储器数据的系统和方法。 存储在主存储器内的数据可以由可能包括一个或多个高速缓存存储器的多个请求者请求。 当主存储器向请求者提供数据时，将以基于请求者最近使用数据的方式提供数据。 例如，如果为数据建立了只读使用模式，则数据将以共享状态返回给请求者。 如果必须更新在共享状态下提供的数据，以便需要请求者返回到主存储器以获得读/写权限，则主存储器此后将以允许写操作完成的独占状态提供数据。 这将继续，直到再次建立只读使用模式。

公开(公告)号：US07047322B1

公开(公告)日：2006-05-16

申请号：US10675784

申请日：2003-09-30

申请人： Mitchell A. Bauman ,  Matthew D. Rench ,  James L. Depenning

发明人： Mitchell A. Bauman ,  Matthew D. Rench ,  James L. Depenning

IPC分类号： G06F13/00

CPC分类号： G06F13/1642 ,  G06F12/0835 ,  G06F12/0897 ,  G06F13/14

摘要： The current invention provides a system and method for managing requests from one or more requesters to one or more resources. These requests, which may be any of multiple request types, are prioritized using one or more threshold values. Each threshold value is associated with one or more of the request types, and defines the maximum number of requests of the associated types that may be pending to the resources before the threshold is reached. When all associated thresholds have been reached for requests of one or more predetermined request types, an indication is provided to re-issue requests of those types at a later time. A priority scheme is used to allow re-issued requests to systematically gain access to the shared resource to prevent the starvation of any given requester.

摘要翻译： 本发明提供了一种用于管理从一个或多个请求者到一个或多个资源的请求的系统和方法。 这些请求可以是多个请求类型中的任何一个，使用一个或多个阈值进行优先级排序。 每个阈值与一个或多个请求类型相关联，并且在达到阈值之前定义可能正在等待资源的关联类型的最大请求数。 当针对一个或多个预定请求类型的请求已经达到所有相关联的阈值时，提供指示以在稍后的时间重发这些类型的请求。 优先权方案用于允许重新发布的请求系统地访问共享资源，以防止任何给定的请求者的饥饿。

公开(公告)号：US06453276B1

公开(公告)日：2002-09-17

申请号：US09218384

申请日：1998-12-22

申请人： Mitchell A. Bauman

发明人： Mitchell A. Bauman

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/3183 ,  G06F17/5022

摘要： A method and apparatus for generating test input for a logic simulator by providing a template that allows a test designer to more efficiently enter the desired test conditions. The template is preferably arranged to facilitate the definition of test cases, and in particular, parallel type test cases. One region of the template is preferably dedicated to one section of a circuit design, and another region is dedicated to another section of the circuit design. When the regions are positioned side-by-side, for example, the test designer can easily identify the test conditions that are applied to the various circuit sections, including the relationships therebetween. Once the test conditions are entered, the template is processed and the desired test input is automatically generated.

摘要翻译： 一种用于通过提供允许测试设计者更有效地输入所需测试条件的模板来生成逻辑模拟器的测试输入的方法和装置。 优选地，该模板被布置为便于测试用例的定义，特别是并行型测试用例。 模板的一个区域优选地专用于电路设计的一个部分，另一个区域专用于电路设计的另一个部分。 例如，当这些区域并排定位时，测试设计者可以容易地识别应用于各个电路部分的测试条件，包括它们之间的关系。 一旦输入测试条件，就会处理模板，并自动生成所需的测试输入。

公开(公告)号：US06336088B1

公开(公告)日：2002-01-01

申请号：US09218812

申请日：1998-12-22

申请人： Mitchell A. Bauman ,  Douglas H. Bloom ,  Joseba M. Desubijan ,  Larry L. Byers

发明人： Mitchell A. Bauman ,  Douglas H. Bloom ,  Joseba M. Desubijan ,  Larry L. Byers

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G01R31/318307 ,  G06F17/5022

摘要： Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is provided for executing each test list, and a run controller is provided for monitoring the execution of each test list. To synchronize the execution of the two or more test lists, the run controller halts the execution of each test list as each test driver assumes a predetermined state. Once all of the test lists are halted, the test lists are synchronized. Once synchronized, selected test drivers are restarted to continue execution of the corresponding test lists in a relatively non-deterministic manner.

摘要翻译： 公开了在期望的同步点同步两个或多个测试列表的执行同时允许测试列表以非确定性方式在同步点之间执行的方法和装置。 提供了用于执行每个测试列表的测试驱动程序，并且提供运行控制器用于监视每个测试列表的执行。 为了同步两个或多个测试列表的执行，运行控制器在每个测试驱动程序采取预定状态时停止每个测试列表的执行。 一旦所有测试列表暂停，测试列表将同步。 一旦同步，重新启动所选的测试驱动程序，以相对非确定性的方式继续执行相应的测试列表。

公开(公告)号：US5860093A

公开(公告)日：1999-01-12

申请号：US785873

申请日：1997-01-21

申请人： Donald C. Englin ,  Mitchell A. Bauman

发明人： Donald C. Englin ,  Mitchell A. Bauman

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0877 ,  G06F12/0851

摘要： Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.

摘要翻译： 用于减少系统控制器中的高速缓存存储器被多个指令处理器访问的系统中的地址/功能传输引脚的方法和装置。 通过使用两个数据传输来获得引脚的减少。 数据寻址时间的增加，否则将使用两个数据传输发生，在第二次数据传输发生时，通过响应第一次数据传输，自身数据传输的时间减少到几乎接近时间。

公开(公告)号：US5822766A

公开(公告)日：1998-10-13

申请号：US780965

申请日：1997-01-09

申请人： David M. Purdham ,  Mitchell A. Bauman

发明人： David M. Purdham ,  Mitchell A. Bauman

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F13/37

CPC分类号： G06F13/1657 ,  G06F13/4256

摘要： An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmits the data set to the next main control logic and coupled memory, which next control logic repeats the process, and which can be continued through a number of coupled control logic units and main memories. A data set includes a header with an address range and function information. If data is to be sent from the storage controller it is appended to the header. Each storage controller compares the address range with the address range of the coupled memory, and if within the address range and for a write, will store the appended data in the header address in the coupled memory. If within the address range and for a read, each storage controller will read the data addressed in the header from the coupled memory and return the data to the storage controller. Because of the direct access these transfer occur at high data rates. The limited number of connections used in this transfer permits accessing main memories on a circuit element using this apparatus and method.

摘要翻译： 一种用于在存储控制器和多个菊花链主存储器之间以高速度在单独的电路元件上传送数据集的装置和方法。 每个主存储器具有从存储控制器接收数据组的耦合控制逻辑，锁存和重新发送数据集到下一个主控制逻辑和耦合存储器，下一个控制逻辑重复该过程，并且可以通过多个 耦合控制逻辑单元和主存储器。 数据集包括具有地址范围和功能信息的报头。 如果要从存储控制器发送数据，则将其附加到标题。 每个存储控制器将地址范围与耦合存储器的地址范围进行比较，如果在地址范围内并且对于写入，则将附加数据存储在耦合存储器中的标题地址中。 如果在地址范围内，并且读取时，每个存储控制器将从耦合的存储器中读取标题中寻址的数据，并将数据返回到存储控制器。 由于直接访问，这些传输以高数据速率发生。 在该传送中使用的有限数量的连接允许使用该装置和方法访问电路元件上的主存储器。

公开(公告)号：US5678026A

公开(公告)日：1997-10-14

申请号：US579896

申请日：1995-12-28

申请人： Kelvin S. Vartti ,  Mitchell A. Bauman

发明人： Kelvin S. Vartti ,  Mitchell A. Bauman

IPC分类号： G06F9/46 ,  G06F13/18 ,  G06F13/362

CPC分类号： G06F9/52 ,  G06F13/18

摘要： A storage lock apparatus for a multiprocessor data processing system. The storage lock apparatus includes control for granting locks to different selectable portions of storage in parallel. In addition, acknowledgment from a remote lock controller is not required for a processor to obtain a lock on an address, even if the address for which the lock was requested is not local relative to the processor. Parallel priority queues are employed for parallel handling of storage lock functions and general storage operations, thereby reducing contention for priority between storage lock operations and general storage operations where there are no addressing conflicts.

摘要翻译： 一种用于多处理器数据处理系统的存储锁定装置。 存储锁定装置包括用于将锁定并行地存储到不同可选择的存储部分的控制。 此外，处理器不需要来自远程锁定控制器的确认来获得地址上的锁定，即使所请求的锁定的地址相对于处理器不是局部的。 并行优先级队列用于并行处理存储锁定功能和一般存储操作，从而减少存储锁定操作与无寻址冲突的一般存储操作之间的优先级争用。

公开(公告)号：US5617375A

公开(公告)日：1997-04-01

申请号：US577908

申请日：1995-12-04

申请人： Mitchell A. Bauman ,  James L. Federici

发明人： Mitchell A. Bauman ,  James L. Federici

IPC分类号： G04G99/00 ,  G06F1/14 ,  G04B47/00 ,  G06F1/04 ,  G06F1/12

CPC分类号： G04G99/006 ,  G06F1/14

摘要： An apparatus for and method of efficiently providing a modular dayclock within a data processing system. This is accomplished by dividing the dayclock hardware into a number of dayclock modules configured to operate in a bit serial fashion. This allows the dayclock to accommodate a variety of dayclock word widths by simply varying the number of dayclock modules provided. Further, since the dayclock may operate serially, rather than in parallel fashion, the number of dayclock module I/O's and board route channels may be substantially reduced. Finally, all control logic may be provided directly in the dayclock modules, thereby eliminating the need for a central dayclock controller.

摘要翻译： 一种在数据处理系统内有效提供模块化时钟的装置和方法。 这通过将日钟硬件分成多个配置为以串行方式操作的日间钟模块来实现。 这样可以通过简单地改变所提供的日时钟模块的数量来使时钟适应各种日时钟字宽。 此外，由于日时钟可以顺序地而不是并行地进行操作，因此可以显着地减少日时钟模块I / O和板路由信道的数量。 最后，所有的控制逻辑可以直接在日时钟模块中提供，从而不需要中央的时钟控制器。