公开(公告)号：US06243803B1

公开(公告)日：2001-06-05

申请号：US09053148

申请日：1998-03-31

Applicant: Mohammad A. Abdallah ,  Vladimir Pentkovski

Inventor： Mohammad A. Abdallah ,  Vladimir Pentkovski

IPC: G06F1500

CPC classification number: G06F7/544 ,  G06F7/5443 ,  G06F9/30021 ,  G06F9/30036 ,  G06F17/10 ,  G06F2207/382 ,  G06F2207/3828 ,  G06F2207/5442

Abstract: A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign bits is produced, each of the third plurality of elements and the plurality of sign bits being computed by subtracting one of a first plurality of elements of a first packed data from a corresponding one of a second plurality of elements of a second packed data. The third plurality of elements and the plurality of sign bits are stored. A fourth packed data having a fourth plurality of elements is produced, each of the fourth plurality of elements being computed by subtracting one of the third plurality of elements from the corresponding one of an at least one element, if the corresponding one of a plurality of sign bits is in a first state; and adding one of the third plurality of elements from the corresponding one of the at least one element, if the corresponding one of the plurality of sign bits is in a second state.

Abstract translation: 一种用于计算封装绝对差异的方法和装置。 根据一种这样的方法和装置，产生具有第三多个元素和多个符号位的第三打包数据，第三多个元素和多个符号位中的每一个通过减去第一多个元素 来自第二打包数据的第二多个元素中的对应的一个的第一打包数据的元素。 存储第三多个元素和多个符号位。 产生具有第四多个元素的第四打包数据，第四多个元素中的每一个通过从至少一个元素中的相应一个元素中减去第三多个元素中的一个来计算，如果多个元素中的相应元素 符号位处于第一状态; 以及如果所述多个符号位中的相应一个位于第二状态，则从所述至少一个元素中的相应一个元素中添加所述第三多个元素之一。

公开(公告)号：US06192467B1

公开(公告)日：2001-02-20

申请号：US09053000

申请日：1998-03-31

Applicant: Mohammad A. Abdallah ,  Vladimir Pentkovski ,  James Coke

Inventor： Mohammad A. Abdallah ,  Vladimir Pentkovski ,  James Coke

IPC: G06F922

CPC classification number: G06F9/3017 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/3822 ,  G06F9/384

Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.

公开(公告)号：US08677105B2

公开(公告)日：2014-03-18

申请号：US12514303

申请日：2007-11-14

Applicant: Mohammad A. Abdallah

Inventor： Mohammad A. Abdallah

IPC: G06F9/46

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

Abstract: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.

Abstract translation: 用于复杂指令格式的动态生成，执行，同步和并行化的统一架构包括虚拟寄存器文件，寄存器高速缓存和寄存器文件层次结构。 自生产和同步动态和静态线程架构提供了有效的上下文切换。

公开(公告)号：US20100161948A1

公开(公告)日：2010-06-24

申请号：US12514303

申请日：2007-11-14

Applicant: Mohammad A. Abdallah

Inventor： Mohammad A. Abdallah

IPC: G06F9/46 ,  G06F9/312

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

Abstract: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.

Abstract translation: 用于复杂指令格式的动态生成，执行，同步和并行化的统一架构包括虚拟寄存器文件，寄存器高速缓存和寄存器文件层次结构。 自生产和同步动态和静态线程架构提供了有效的上下文切换。

公开(公告)号：US07480360B2

公开(公告)日：2009-01-20

申请号：US11124553

申请日：2005-05-06

Applicant: Bruce Querbach ,  Mohammad A. Abdallah ,  Amjad M. A. Khan ,  Mir M. Hossain ,  Sanjib M. Sarkar

Inventor： Bruce Querbach ,  Mohammad A. Abdallah ,  Amjad M. A. Khan ,  Mir M. Hossain ,  Sanjib M. Sarkar

IPC: H04L7/00

CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

Abstract translation: 一种技术包括响应于训练模式，通过总线的数据位线在计算机系统的设备和处理器之间进行通信。 该技术包括基于通信，调节选通信号和通过数据位线传播的信号之间的定时。

公开(公告)号：US06718440B2

公开(公告)日：2004-04-06

申请号：US09966587

申请日：2001-09-28

Applicant: Subramaniam Maiyuran ,  Vivek Garg ,  Mohammad A. Abdallah ,  Jagannath Keshava

Inventor： Subramaniam Maiyuran ,  Vivek Garg ,  Mohammad A. Abdallah ,  Jagannath Keshava

IPC: G06F1200

CPC classification number: G06F9/3802 ,  G06F9/383 ,  G06F12/0862 ,  G06F2212/6028

Abstract: A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

Abstract translation: 在识别所请求的数据和/或一个或多个指令是否在第一存储器中之前或之前发出请求提示。 访问第二存储器以响应于请求提示来获取数据和/或一个或多个指令。 从第二存储器访问的数据和/或指令被存储在缓冲器中。 如果请求的数据和/或指令不在第一存储器中，则从缓冲器返回数据和/或指令。

公开(公告)号：US06701414B2

公开(公告)日：2004-03-02

申请号：US10427908

申请日：2003-05-02

Applicant: Mohammad A. Abdallah ,  Khalid Al-Dajani

Inventor： Mohammad A. Abdallah ,  Khalid Al-Dajani

IPC: G06F1200

CPC classification number: G06F9/383 ,  G06F9/3455 ,  G06F9/3832 ,  G06F12/0862 ,  G06F2212/6026

Abstract: A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

Abstract translation: 基于由指令引起的高速缓存未命中的距离预取指令的数据的预取器。 在一个实施例中，预取器包括存储器，用于存储预取表，其包含包含由指令引起的高速缓存未命中之间的距离的一个或多个条目。 在另一个实施例中，预取数据元素的地址是基于记录在指令的预取表中的高速缓存未命中之间的距离来确定的。