公开(公告)号：US20140040543A1

公开(公告)日：2014-02-06

申请号：US14048451

申请日：2013-10-08

Applicant: Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G11C7/10

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

公开(公告)号：US20130151930A1

公开(公告)日：2013-06-13

申请号：US13323405

申请日：2011-12-12

Applicant: Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

Inventor： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

IPC: G06F11/10

CPC classification number: G06F11/2236

Abstract: In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。

公开(公告)号：US08145732B2

公开(公告)日：2012-03-27

申请号：US11284537

申请日：2005-11-21

Applicant: Mohan J. Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

Inventor： Mohan J. Kumar ,  Murugasamy Nachimuthu ,  Allen Baum

IPC: G06F15/177 ,  G06F15/173 ,  G06F15/16 ,  G06F11/00 ,  G06F9/44 ,  G06F9/445 ,  H04L12/28 ,  H04B1/38 ,  G06Q10/00 ,  G06Q30/00

CPC classification number: H04L41/082

Abstract: A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.

Abstract translation: 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

公开(公告)号：US20110161676A1

公开(公告)日：2011-06-30

申请号：US12650579

申请日：2009-12-31

Applicant: Sham M. Datta ,  Ernie F. Brickell ,  Mohan J. Kumar

Inventor： Sham M. Datta ,  Ernie F. Brickell ,  Mohan J. Kumar

IPC: G06F21/00

CPC classification number: G06F21/00 ,  G06F21/57 ,  G06F21/572 ,  G06F21/71 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: Systems, apparatuses, and methods, and for entering a secured system environment using multiple authenticated code modules are disclosed. In one embodiment, a processor includes a decoder and control logic. The decoder is to decode a secured enter instruction. The control logic is to find an entry corresponding to the processor in a match table in a master authenticated code module and to read a master header and an individual authenticated code module from the master authenticated code module in response to decoding the secured enter instruction.

Abstract translation: 公开了系统，装置和方法以及使用多个认证代码模块输入安全系统环境。 在一个实施例中，处理器包括解码器和控制逻辑。 解码器是对安全的输入指令进行解码。 控制逻辑是在主认证代码模块的匹配表中找到与处理器相对应的条目，并且响应于对安全的进入指令进行解码，从主认证代码模块读取主标题和单独的认证代码模块。

公开(公告)号：US07673090B2

公开(公告)日：2010-03-02

申请号：US10028858

申请日：2001-12-19

Applicant: Shivnandan D. Kaushik ,  Ling Cen ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

Inventor： Shivnandan D. Kaushik ,  Ling Cen ,  James B. Crossland ,  Mohan J. Kumar ,  Linda J. Rankin ,  David J. O'Shea

IPC: H05K7/10 ,  G06F13/24 ,  G06F13/32 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/4081

Abstract: Hot plug modules comprising processors, memory, and/or I/O hubs may be added to and removed from a running computing device without rebooting the running computing device. The hot plug modules and computing device comprise hot plug interfaces that support hot plug addition and hot plug removal of the hot plug modules.

Abstract translation: 包括处理器，存储器和/或I / O集线器的热插拔模块可以被添加到正在运行的计算设备和从运行的计算设备移除，而不需要重新启动正在运行的计算设备。 热插拔模块和计算设备包括热插拔接口，其支持热插拔模块和热插拔模块的热插拔。

公开(公告)号：US20090172372A1

公开(公告)日：2009-07-02

申请号：US11967299

申请日：2007-12-31

Applicant: Mohan J. Kumar ,  Sarathy Jayakumar ,  Sham Datta

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Sham Datta

IPC: G06F9/26

CPC classification number: G06F9/4812

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract translation: 一种方法包括确定多个存储器地址，每个存储器地址彼此不同。 该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。 该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。 还公开了一种相关的机器可读介质。

公开(公告)号：US20090006793A1

公开(公告)日：2009-01-01

申请号：US11772158

申请日：2007-06-30

Applicant: Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

Inventor： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

IPC: G06F12/16

CPC classification number: G06F11/1658 ,  G06F11/1666 ,  G06F11/20

Abstract: In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

Abstract translation: 在用于在运行时期间切换到备用存储器模块的方法中，处理系统确定应停止在处理系统中的有效存储器模块的利用。 然后，处理系统可以激活镜像复制模式，当在活动存储器模块中访问数据时，使得处理系统中的存储器控​​制器将数据从活动存储器模块复制到备用存储器模块。 然后，处理系统中的操作系统（OS）可以访问活动存储器模块中的数据，以使存储器控制器将数据从有源存储器模块复制到备用存储器模块。 然后，处理系统可以重新配置存储器控制器，以便直接读取和写入备用存储器模块而不是有源存储器模块。 描述和要求保护其他实施例。

公开(公告)号：US07376775B2

公开(公告)日：2008-05-20

申请号：US10749929

申请日：2003-12-29

Applicant: Lily Pao Looi ,  Stanley Steven Kulick ,  Dean A Mulla ,  Ashish Gupta ,  Keith R. Pflederer ,  Shivnandan D. Kaushik ,  Mohan J. Kumar ,  James B. Crossland

Inventor： Lily Pao Looi ,  Stanley Steven Kulick ,  Dean A Mulla ,  Ashish Gupta ,  Keith R. Pflederer ,  Shivnandan D. Kaushik ,  Mohan J. Kumar ,  James B. Crossland

IPC: G06F13/00

CPC classification number: G06F11/1666 ,  G06F13/16

Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

Abstract translation: 在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟 一个扩展记忆桥。 在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。

公开(公告)号：US20070277223A1

公开(公告)日：2007-11-29

申请号：US11442230

申请日：2006-05-26

Applicant: Shamanna M. Datta ,  Mohan J. Kumar

Inventor： Shamanna M. Datta ,  Mohan J. Kumar

IPC: H04L9/32

CPC classification number: G06F21/53 ,  G06F21/00 ,  G06F21/74 ,  G06F21/85

Abstract: Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

Abstract translation: 描述了在微处理器系统中启动安全操作的方法和装置。 在一个实施例中，系统包括执行安全输入指令的处理器和芯片组，以使系统在执行安全输入指令期间进入静止状态。

公开(公告)号：US06308227B1

公开(公告)日：2001-10-23

申请号：US09103764

申请日：1998-06-24

Applicant: Mohan J. Kumar ,  Rajiv Choudhary

Inventor： Mohan J. Kumar ,  Rajiv Choudhary

IPC: G06F1314

CPC classification number: H04L61/2092 ,  H04L29/06 ,  H04L29/1232 ,  H04L67/14 ,  H04L69/329 ,  H04W8/26 ,  H04W40/246

Abstract: A persistent host identifier value is used during the automatic detection (e.g., enumeration) of a wireless peripheral device by a host computer system following a power-up or reset operation of the host. Use of the persistent host identifier may allow the rapid establishment of a communication channel between the host computer system and wireless peripheral device. Once a wireless peripheral device has been enumerated, an identifier value associated with the peripheral device may also be retained, and used, during subsequent enumeration and/or binding operations.

Abstract translation: 在主机的上电或复位操作之后，由主计算机系统在无线外围设备的自动检测（例如枚举）期间使用持久主机标识符值。 使用持久主机标识符可以允许在主计算机系统和无线外围设备之间快速建立通信信道。 一旦无线外围设备被枚举，与外围设备相关联的标识符值也可以在后续的枚举和/或绑定操作期间被保留和使用。