公开(公告)号：US08296768B2

公开(公告)日：2012-10-23

申请号：US11772155

申请日：2007-06-30

申请人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

发明人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

IPC分类号： G06F9/46 ,  G06F11/00

CPC分类号： G06F11/2028 ,  G06F11/203 ,  G06F11/2051

摘要： In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

摘要翻译： 在运行时切换到备用处理器的方法中，处理系统确定执行应当从有源处理器迁移。 然后暂停操作系统（OS）调度器和至少一个设备，并且活动处理器进入空闲状态。 有源处理器中的可写和基本不可写存储器的状态数据被加载到备用处理器中。 用于处理系统的中断路由表逻辑被动态重新编程，以将外部中断引导到备用处理器。 然后，活动处理器可以被排除在外，并且设备和OS调度器可以被取消启动或恢复。 然后可以将线程分派到备用处理器执行。 描述和要求保护其他实施例。

公开(公告)号：US20090006793A1

公开(公告)日：2009-01-01

申请号：US11772158

申请日：2007-06-30

申请人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

发明人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

IPC分类号： G06F12/16

CPC分类号： G06F11/1658 ,  G06F11/1666 ,  G06F11/20

摘要： In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

摘要翻译： 在用于在运行时期间切换到备用存储器模块的方法中，处理系统确定应停止在处理系统中的有效存储器模块的利用。 然后，处理系统可以激活镜像复制模式，当在活动存储器模块中访问数据时，使得处理系统中的存储器控​​制器将数据从活动存储器模块复制到备用存储器模块。 然后，处理系统中的操作系统（OS）可以访问活动存储器模块中的数据，以使存储器控制器将数据从有源存储器模块复制到备用存储器模块。 然后，处理系统可以重新配置存储器控制器，以便直接读取和写入备用存储器模块而不是有源存储器模块。 描述和要求保护其他实施例。

公开(公告)号：US20090007121A1

公开(公告)日：2009-01-01

申请号：US11772155

申请日：2007-06-30

申请人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

发明人： Koichi Yamada ,  Douglas E. Covelli ,  Jose A. Vargas ,  Mohan J. Kumar

IPC分类号： G06F9/46

CPC分类号： G06F11/2028 ,  G06F11/203 ,  G06F11/2051

摘要： In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

摘要翻译： 在运行时切换到备用处理器的方法中，处理系统确定执行应当从有源处理器迁移。 然后暂停操作系统（OS）调度器和至少一个设备，并且活动处理器进入空闲状态。 有源处理器中的可写和基本不可写存储器的状态数据被加载到备用处理器中。 用于处理系统的中断路由表逻辑被动态重新编程，以将外部中断引导到备用处理器。 然后，活动处理器可以被排除在外，并且设备和OS调度器可以被取消启动或恢复。 然后可以将线程分派到备用处理器执行。 描述和要求保护其他实施例。

公开(公告)号：US07546487B2

公开(公告)日：2009-06-09

申请号：US11227831

申请日：2005-09-15

申请人： Suresh Marisetty ,  Andrew J. Fish ,  Koichi Yamada ,  Scott D. Brenden ,  James B. Crossland ,  Shivnandan Kaushik ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Suresh Marisetty ,  Andrew J. Fish ,  Koichi Yamada ,  Scott D. Brenden ,  James B. Crossland ,  Shivnandan Kaushik ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/0793 ,  G06F11/0706

摘要： Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

摘要翻译： 使用协调操作系统（OS）和固件服务执行硬件错误处理的方法和架构。 在一个方面，提供固件接口以使OS能够访问固件错误处理服务。 这样的服务使得OS能够访问有关平台硬件错误的错误数据，这些错误数据可能不会通过平台处理器或其他常规方法被定向访问。 还公开了用于在使用基于OS的服务尝试服务错误之前拦截硬件错误事件的处理以及将控制引导到固件错误处理服务的技术。 固件服务可以纠正OS稍后访问或使用带外通信信道提供给远程管理服务器的硬件错误和/或日志错误数据。 根据另一方面，固件拦截和服务可以以对OS是透明的方式来执行。

公开(公告)号：US08645797B2

公开(公告)日：2014-02-04

申请号：US13323405

申请日：2011-12-12

申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G11C29/00

CPC分类号： G06F11/2236

摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。

公开(公告)号：US20130339829A1

公开(公告)日：2013-12-19

申请号：US13995458

申请日：2011-12-29

申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

IPC分类号： G06F11/10

CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：US09405646B2

公开(公告)日：2016-08-02

申请号：US13992506

申请日：2011-09-29

申请人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

发明人： Theodros Yigzaw ,  Kai Cheng ,  Mohan J. Kumar ,  Jose A. Vargas ,  Gopikrishna Jandhyala

IPC分类号： G06F11/00 ,  G06F11/263 ,  G06F11/36

CPC分类号： G06F11/263 ,  G06F11/3664 ,  G06F11/3688

摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

摘要翻译： 公开了一种向存储器注入错误的装置和方法。 在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。 如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

公开(公告)号：US20130332781A1

公开(公告)日：2013-12-12

申请号：US13997870

申请日：2012-06-06

申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G06F11/07

CPC分类号： G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

摘要翻译： 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

申请人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

发明人： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/10

摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20130151930A1

公开(公告)日：2013-06-13

申请号：US13323405

申请日：2011-12-12

申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

IPC分类号： G06F11/10

CPC分类号： G06F11/2236

摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。