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公开(公告)号：US08145732B2
公开(公告)日：2012-03-27
申请号：US11284537
申请日：2005-11-21
IPC分类号： G06F15/177 , G06F15/173 , G06F15/16 , G06F11/00 , G06F9/44 , G06F9/445 , H04L12/28 , H04B1/38 , G06Q10/00 , G06Q30/00
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译： 描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为 由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。 程序代码的每个实例都要由发送到的特定组件来执行。 程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。
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2.发明授权Systems and methods for implementing reliability, availability and serviceability in a computer system 失效在计算机系统中实现可靠性，可用性和可维护性的系统和方法公开(公告)号：US07555671B2
公开(公告)日：2009-06-30
申请号：US11513872
申请日：2006-08-31
IPC分类号： G06F11/00
CPC分类号： G06F9/4812
摘要： Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.
摘要翻译： 实施例包括用于处理计算机系统中的可靠性，可用性和可服务性（RAS）事件的系统和方法。 实施例包括处理管理中断（MI）周期的第一部分中的关键事件。 MI周期被选择为不大于最大容许的操作系统（OS）等待时间周期。 如果在处理关键事件之后的时间内仍处于当前的MI周期，则系统在当前MI周期的剩余时间内处理非关键事件。 如果在目前的MI期结束时，一些非关键事件仍然待处理，则随后的MI期间被安排处理剩余的非关键事件。
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公开(公告)号：US07472266B2
公开(公告)日：2008-12-30
申请号：US11322997
申请日：2005-12-30
CPC分类号： G06F11/1417 , G06F11/0724 , G06F11/0757
摘要： In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，监视多处理器系统中的系统引导带处理器的引导进程，并且使用应用处理器检测引导处理器故障。 如果检测到引导处理器故障，系统的至少一部分将被重新初始化（和/或系统重新启动）。 描述和要求保护其他实施例。
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4.发明申请Systems and methods for implementing reliability, availability and serviceability in a computer system 失效在计算机系统中实现可靠性，可用性和可维护性的系统和方法公开(公告)号：US20080115138A1
公开(公告)日：2008-05-15
申请号：US11513872
申请日：2006-08-31
IPC分类号： G06F9/46
CPC分类号： G06F9/4812
摘要： Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.
摘要翻译： 实施例包括用于处理计算机系统中的可靠性，可用性和可服务性（RAS）事件的系统和方法。 实施例包括处理管理中断（MI）周期的第一部分中的关键事件。 MI周期被选择为不大于最大容许的操作系统（OS）等待时间周期。 如果在处理关键事件之后的时间内仍处于当前的MI周期，则系统在当前MI周期的剩余时间内处理非关键事件。 如果在目前的MI期结束时，一些非关键事件仍然待处理，则随后的MI期间被安排处理剩余的非关键事件。
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公开(公告)号：US09342394B2
公开(公告)日：2016-05-17
申请号：US13997301
申请日：2011-12-29
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/3664 , G06F21/57
摘要： Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.
摘要翻译： 本文描述了各种实施例。 一些实施例包括操作系统和平台。 该平台包括具有错误寄存器的处理器。 操作系统只能通过平台以安全的方式（例如使用平台固件）写入错误寄存器。 描述和要求保护其他实施例。
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公开(公告)号：US20210096848A1
公开(公告)日：2021-04-01
申请号：US17120072
申请日：2020-12-11
申请人： Sarathy Jayakumar , Chuan Song , Mohan J. Kumar
发明人： Sarathy Jayakumar , Chuan Song , Mohan J. Kumar
IPC分类号： G06F8/656 , G06F9/48 , G06F9/4401 , G06F9/455 , G06F12/1027
摘要： A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.
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公开(公告)号：US20200285461A1
公开(公告)日：2020-09-10
申请号：US16841410
申请日：2020-04-06
申请人： Mohan J. Kumar , Sarathy Jayakumar , Chuan Song , Ruixia Li , Xiaojin Yuan , Haiyue Wang , Chong Han
发明人： Mohan J. Kumar , Sarathy Jayakumar , Chuan Song , Ruixia Li , Xiaojin Yuan , Haiyue Wang , Chong Han
IPC分类号： G06F8/656 , G06F8/654 , G06F9/4401 , G06F9/445
摘要： A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.
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公开(公告)号：US10223204B2
公开(公告)日：2019-03-05
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
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公开(公告)号：US20180089130A1
公开(公告)日：2018-03-29
申请号：US15274656
申请日：2016-09-23
摘要： A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.
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公开(公告)号：US20170289256A1
公开(公告)日：2017-10-05
申请号：US15089377
申请日：2016-04-01
IPC分类号： H04L29/08 , H04L29/06 , H04L12/24 , H04L12/46 , H04L12/931
CPC分类号： H04L67/125 , G06F1/20 , H04L12/4641 , H04L41/0668 , H04L41/0695 , H04L41/12 , H04L43/08 , H04L43/0817 , H04L43/10 , H04L49/70 , H04L63/08 , H04L67/02 , H04L67/10 , H04L67/1095 , H04L67/1097 , H04L67/12 , H04L69/40
摘要： Methods and apparatus for highly available rack management in Rack Scale environment. Rack Management Modules (RMMs) are configured to manage power and thermal zones in a rack including a plurality of pooled system drawers, wherein each pooled system drawer is associated with a respective power zone including power sensors and power control devices and a respective thermal zone including thermal sensors and thermal devices. During operation, one of the RMMs is implemented as a master RMM, and the other is implemented as a slave RMM. The master RMM is used to monitor the power and thermal zones. State information is periodically synchronized between the master RMM and the slave RMM. The RMMs are further configured to perform a fail-over operation in connection with a failed or failing RMM, where after the fail-over operation the slave becomes the new master RMM and the previous master RMM becomes the new slave.
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