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49 条记录 (耗时 0.024 秒)

    Injecting a data error into a writeback path to memory
    1.
    发明授权
    Injecting a data error into a writeback path to memory 有权
    将数据错误注入到内存的回写路径中

    公开(公告)号：US08645797B2

    公开(公告)日：2014-02-04

    申请号：US13323405

    申请日：2011-12-12

    申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

    发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

    IPC分类号： G11C29/00

    CPC分类号： G06F11/2236

    摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。

    Injecting A Data Error Into A Writeback Path To Memory
    2.
    发明申请
    Injecting A Data Error Into A Writeback Path To Memory 有权
    将数据错误注入到内存的回写路径中

    公开(公告)号：US20130151930A1

    公开(公告)日：2013-06-13

    申请号：US13323405

    申请日：2011-12-12

    申请人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

    发明人： Theodros Yigzaw ,  Yen-Cheng Liu ,  Mohan J. Kumar ,  Jose A. Vargas

    IPC分类号： G06F11/10

    CPC分类号： G06F11/2236

    摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。 软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。 该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到 响应于指令的检测而在系统存储器内的地址。 描述和要求保护其他实施例。

    APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF MESSAGES
    7.
    发明申请
    APPARATUS, SYSTEM, AND METHODS FOR FACILITATING ONE-WAY ORDERING OF MESSAGES 有权
    设备，系统和方法，促进消息的单向订购

    公开(公告)号：US20120079032A1

    公开(公告)日：2012-03-29

    申请号：US12889802

    申请日：2010-09-24

    申请人： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

    发明人： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

    IPC分类号： G06F15/16 ,  G06F5/00 ,  G06F12/08

    CPC分类号： H04L67/10 ,  G06F15/17325

    摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.

    摘要翻译： 用于促进独立消息类别的单向排序的方法，装置和系统。 单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。 在一个方面，第二消息类的消息可能不会传递第一消息类的消息。 此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

    Preventing system snoop and cross-snoop conflicts
    9.
    发明授权
    Preventing system snoop and cross-snoop conflicts 有权
    防止系统侦听和交叉侦听冲突

    公开(公告)号：US07689778B2

    公开(公告)日：2010-03-30

    申请号：US11000768

    申请日：2004-11-30

    申请人： Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  George Cai ,  Jeffrey D. Gilbert

    发明人： Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  George Cai ,  Jeffrey D. Gilbert

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0831

    摘要： In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

    摘要翻译： 在各种实施例中，可以使用硬件，软件和固件或其组合来防止微处理器和/或计算机系统内的高速缓存冲突。 更具体地，本发明的实施例涉及一种防止处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。

    Preventing system snoop and cross-snoop conflicts
    10.
    发明申请
    Preventing system snoop and cross-snoop conflicts 有权
    防止系统侦听和交叉侦听冲突

    公开(公告)号：US20060117148A1

    公开(公告)日：2006-06-01

    申请号：US11000768

    申请日：2004-11-30

    申请人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai ,  Jeffrey Gilbert

    发明人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai ,  Jeffrey Gilbert

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0831

    摘要： Preventing cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

    摘要翻译： 防止微处理器和/或计算机系统中的缓存冲突。 更具体地，本发明的实施例涉及一种防止处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。