公开(公告)号：US20090157968A1

公开(公告)日：2009-06-18

申请号：US11954936

申请日：2007-12-12

申请人： Gordon B. Bell ,  Anil Krishna ,  Nicholas D. Lindbert ,  Ken V. Vu

发明人： Gordon B. Bell ,  Anil Krishna ,  Nicholas D. Lindbert ,  Ken V. Vu

IPC分类号： G06F12/08

CPC分类号： G06F12/0864

摘要： A cache memory including a plurality of sets of cache lines, and providing an implementation for increasing the associativity of selected sets of cache lines including the combination of providing a group of parameters for determining the worthiness of a cache line stored in a basic set of cache lines, providing a partner set of cache lines, in the cache memory, associated with the basic set, applying the group of parameters to determine the worthiness level of a cache line in the basic set and responsive to a determination of a worthiness in excess of a predetermined level, for a cache line, storing said worthiness level cache line in said partner set.

摘要翻译： 一种高速缓冲存储器，包括多组高速缓存行，并且提供用于增加所选择的高速缓存行集合的关联性的实现，包括提供用于确定存储在基本高速缓存中的高速缓存行的价值的一组参数的组合 在高速缓冲存储器中提供与基本集合相关联的一组高速缓存行，应用该组参数以确定基本集合中的高速缓存行的有效性水平，并且响应于超过 用于高速缓存行的预定级别，将所述有价值级别的高速缓存行存储在所述伙伴集合中。

公开(公告)号：US09262170B2

公开(公告)日：2016-02-16

申请号：US13558750

申请日：2012-07-26

申请人： Anil Krishna ,  Ganesh Balakrishnan ,  Gordon B. Bell

发明人： Anil Krishna ,  Ganesh Balakrishnan ,  Gordon B. Bell

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F11/14

CPC分类号： G06F9/3836 ,  G06F9/3859 ,  G06F9/3863 ,  G06F11/1407

摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.

摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。

公开(公告)号：US20140032884A1

公开(公告)日：2014-01-30

申请号：US13558750

申请日：2012-07-26

申请人： Anil Krishna ,  Ganesh Balakrishnan ,  Gordon B. Bell

发明人： Anil Krishna ,  Ganesh Balakrishnan ,  Gordon B. Bell

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3859 ,  G06F9/3863 ,  G06F11/1407

摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.

摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。

公开(公告)号：US20130297853A1

公开(公告)日：2013-11-07

申请号：US13464084

申请日：2012-05-04

申请人： Ganesh Balakrishnan ,  Anil Krishna

发明人： Ganesh Balakrishnan ,  Anil Krishna

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F2212/222 ,  G06F2212/40 ,  Y02D10/13

摘要： In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.

摘要翻译： 在将数据存储在闪存阵列中的方法中，闪存阵列包括多个物理页。 该方法包括通过通信总线接收执行数据访问操作的请求。 该请求包括数据和逻辑页面地址。 该方法还包括分配闪存阵列的一个或多个物理页面以执行数据访问操作。 该方法还包括基于闪速存储器阵列的历史使用数据，选择性地将包含在逻辑页面中的数据编码到一个或多个物理页面中。

公开(公告)号：US08364898B2

公开(公告)日：2013-01-29

申请号：US12358873

申请日：2009-01-23

申请人： Ganesh Balakrishnan ,  Anil Krishna

发明人： Ganesh Balakrishnan ,  Anil Krishna

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/123

摘要： A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations.

摘要翻译： 一种用于利用最近使用的（LRU）比特和存在比特来选择用于从处理器存储器子系统中的较低级高速缓存进行逐出的高速缓存线的方法和系统。 缓存返回无效（CBI）逻辑利用LRU位来驱逐LRU组内的高速缓存行，跟随低级缓存中的高速缓存未命中。 此外，CBI逻辑使用存在位来（a）指示较低级高速缓存中的高速缓存行是否也存在于较高级高速缓存中，并且（b）仅驱逐不存在的较低级高速缓存中的高速缓存行 在相应的较高级缓存中。 然而，当选择用于逐出的较低级高速缓存行也存在于任何更高级别的高速缓存中时，CBI逻辑使高级缓存中的高速缓存行无效。 驱逐和无效后，CBI逻辑适当地更新存在位和LRU位的值。

公开(公告)号：US08200905B2

公开(公告)日：2012-06-12

申请号：US12192072

申请日：2008-08-14

申请人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

发明人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0831 ,  G06F2212/6026

摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

公开(公告)号：US08140825B2

公开(公告)日：2012-03-20

申请号：US12185964

申请日：2008-08-05

申请人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

发明人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F12/0215

摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。

公开(公告)号：US20100037034A1

公开(公告)日：2010-02-11

申请号：US12185964

申请日：2008-08-05

申请人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

发明人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

IPC分类号： G06F12/10

CPC分类号： G06F12/0215

摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。

公开(公告)号：US08639886B2

公开(公告)日：2014-01-28

申请号：US12364984

申请日：2009-02-03

申请人： Gordon Bell ,  Anil Krishna ,  Srinivasan Ramani

发明人： Gordon Bell ,  Anil Krishna ,  Srinivasan Ramani

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3857

摘要： A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.

摘要翻译： 一种用于在不使用单独的显式跑道缓存结构的情况下优化处理器的跑步头操作的系统和方法。 尽管存储指令不允许更新处理器缓存和系统存储器，但存储指令将其结果写入现有的处理器存储队列中，而不是简单地将存储指令放在处理器跑头模式中。 在跑步模式期间使用存储队列来保存存储指令结果允许更多的最新跑步加载指令来搜索存储队列中的退出存储队列条目以匹配地址以利用来自已退休但仍可搜索的存储指令的数据。 退休存储指令可以是退出存储指令退出，或退出存储指令，在进入排头模式之前执行。

公开(公告)号：US08438339B2

公开(公告)日：2013-05-07

申请号：US12633976

申请日：2009-12-09

申请人： Anil Krishna ,  Brian M. Rogers

发明人： Anil Krishna ,  Brian M. Rogers

IPC分类号： G06F12/00

CPC分类号： G06F12/0842

摘要： The illustrative embodiments provide a method, a computer program product, and an apparatus for managing a cache. A probability of a future request for data to be stored in a portion of the cache by a thread is identified for each of the number of threads to form a number of probabilities. The data is stored with a rank in a number of ranks in the portion of the cache responsive to receiving the future request from the thread in the number of threads for the data. The rank is selected using the probability in the number of probabilities for the thread.

摘要翻译： 说明性实施例提供了一种方法，计算机程序产品和用于管理高速缓存的装置。 针对线程数量的每一个标识未来要求将数据存储在线程的一部分缓存中的概率，以形成多个概率。 该数据以缓存部分中的多个等级排列存储，响应于在数据线程中从线程接收将来的请求。 使用线程概率的概率来选择等级。