公开(公告)号：US20180102742A1

公开(公告)日：2018-04-12

申请号：US15840414

申请日：2017-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yusuke SHIMAMUNE ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Hayato NAKAMURA ,  Kazuhito NAKAI ,  Fuminori MORISAWA

IPC: H03F1/02 ,  H03F3/193 ,  H03F1/30 ,  H03F3/191 ,  H03F3/21 ,  H03F3/04

CPC classification number: H03F1/0222 ,  G05F3/262 ,  H03F1/301 ,  H03F1/302 ,  H03F3/04 ,  H03F3/191 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/18 ,  H03F2200/451

Abstract: Provided is a current output circuit that includes: a first FET that has a power supply voltage supplied to a source thereof, that has a first voltage supplied to a gate thereof and that outputs a first current from a drain thereof; a second FET that has the power supply voltage supplied to a source thereof, that has the first voltage supplied to a gate thereof and that outputs an output current from a drain thereof; a first control circuit that controls the first voltage such that the first current comes to be at a target level; and a second control circuit that performs control such that a drain voltage of the first FET and a drain voltage of the second FET are made equal to each other.

公开(公告)号：US20190326865A1

公开(公告)日：2019-10-24

申请号：US16364324

申请日：2019-03-26

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takeyuki OKABE ,  Fuminori MORISAWA ,  Mizuho ISHIKAWA ,  Yuri HONDA

IPC: H03F3/21 ,  H03F1/02 ,  H03F3/213

Abstract: A control circuit includes a first output unit configured to output a constant bias current for setting an electrical bias state of a bias circuit to the bias circuit; a second output unit configured to output a bias control current or constant voltage for controlling the electrical bias state of the bias circuit to the bias circuit; a resistor having one end connected to a reference potential; and a switch provided between another end of the resistor and an output terminal of the second output unit.

公开(公告)号：US20180152151A1

公开(公告)日：2018-05-31

申请号：US15871275

申请日：2018-01-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshiaki HARASAWA ,  Fuminori MORISAWA

IPC: H03F1/30 ,  H03F3/24

CPC classification number: H03F1/30 ,  G05F3/20 ,  H03F1/301 ,  H03F3/245 ,  H03F2200/451 ,  H03F2200/528 ,  H03F2200/555

Abstract: Provided is a bias control circuit that includes: a reference voltage circuit that generates a reference voltage; a resistor; a temperature dependent current generating circuit that generates a temperature dependent current, which changes depending on temperature, on the basis of the reference voltage and that supplies the temperature dependent current to one end of the resistor; a reference voltage buffer circuit that applies the reference voltage to the other end of the resistor; a constant current generating circuit that generates a constant current, which is for driving the reference voltage buffer circuit, on the basis of the reference voltage and that supplies the constant current to the other end of the resistor; and a bias generating circuit that generates a bias voltage or a bias current for a power amplification circuit on the basis of the voltage at the one end of the resistor.

公开(公告)号：US20170099033A1

公开(公告)日：2017-04-06

申请号：US15274539

申请日：2016-09-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yusuke SHIMAMUNE ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Hayato NAKAMURA ,  Kazuhito NAKAI ,  Fuminori MORISAWA

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/193

CPC classification number: H03F1/0222 ,  G05F3/262 ,  H03F1/301 ,  H03F1/302 ,  H03F3/04 ,  H03F3/191 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/18 ,  H03F2200/451

Abstract: Provided is a current output circuit that includes: a first FET that has a power supply voltage supplied to a source thereof, that has a first voltage supplied to a gate thereof and that outputs a first current from a drain thereof; a second FET that has the power supply voltage supplied to a source thereof, that has the first voltage supplied to a gate thereof and that outputs an output current from a drain thereof; a first control circuit that controls the first voltage such that the first current comes to be at a target level; and a second control circuit that performs control such that a drain voltage of the first FET and a drain voltage of the second FET are made equal to each other.