公开(公告)号：US12113069B2

公开(公告)日：2024-10-08

申请号：US17901189

申请日：2022-09-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Richard James Dowling ,  Hiroshi Yamada ,  Alain Duvallet ,  Ronald Eugene Reedy

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/373 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/4882 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/3735 ,  H01L27/092

Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

公开(公告)号：US12062669B2

公开(公告)日：2024-08-13

申请号：US18313826

申请日：2023-05-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Abhijeet Paul ,  Hiroshi Yamada ,  Alain Duvallet

IPC: H01L27/13 ,  H01L21/762 ,  H01L21/84 ,  H01L49/02

CPC classification number: H01L27/13 ,  H01L21/76251 ,  H01L21/84 ,  H01L28/60

Abstract: FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections

公开(公告)号：US10374569B2

公开(公告)日：2019-08-06

申请号：US15941095

申请日：2018-03-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keiichi Umeda ,  Takehiko Kishi ,  Hiroshi Yamada ,  Masakazu Fukumitsu

IPC: H03H3/007 ,  H03H9/05 ,  H03H3/04 ,  H03H9/10 ,  H03H9/24

Abstract: A resonance device that includes a lower cover formed from non-degenerate silicon; a resonator having a degenerate silicon substrate with a lower surface facing the lower cover, and including first and second electrode layers laminated on the substrate with a piezoelectric film formed therebetween and having a surface opposing an upper surface of the substrate. Moreover, the lower surface of the substrate has an adjustment region where a depth or height of projections and recesses formed on the surface is larger than that in another region of the lower surface of the substrate or is a region where an area of the projections and recesses is larger than that in the other region of the lower surface of the substrate.

公开(公告)号：US20240421225A1

公开(公告)日：2024-12-19

申请号：US18335641

申请日：2023-06-15

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jagar Singh ,  Anil Kumar ,  Sinan Goktepeli ,  Hiroshi Yamada ,  Akira Fujihara ,  Tsunekazu Saimei ,  Kazuhiko Shibata

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.

公开(公告)号：US20160072473A1

公开(公告)日：2016-03-10

申请号：US14933336

申请日：2015-11-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toshio Nishimura ,  Takashi Hase ,  Keisuke Takeyama ,  Hiroaki Kaida ,  Keiichi Umeda ,  Takehiko Kishi ,  Hiroshi Yamada

IPC: H03H9/21

CPC classification number: H03H9/21

Abstract: A vibrating device having a number 2N (N is an integer equal to 2 or larger) of tuning fork arms extending in a first direction are arranged side by side in a second direction. Phases of flexural vibrations of the number N of tuning fork arms positioned at a first side of an imaginary line A, which passes a center of a region in the second direction where the number 2N of tuning fork arms are disposed and which extends in the first direction, are symmetric to phases of flexural vibrations of the number N of tuning fork arms positioned at a second side of the imaginary line opposite the first side.

Abstract translation: 具有沿第一方向延伸的音叉臂的数量为2N（N是等于2或更大的整数）的振动装置在第二方向上并排布置。 定位在假想线A的第一侧的音叉臂数量N的弯曲振动相位，该假想线A的第二方向的中心位于音叉臂的数目2N的第二方向上，并且在第一方向上延伸 方向，对称于位于与第一侧相对的假想线的第二侧的音叉臂数量N的弯曲振动的相位。