公开(公告)号：US20210083080A1

公开(公告)日：2021-03-18

申请号：US17002618

申请日：2020-08-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Yasunari UMEMOTO ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI ,  Masao KONDO

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L27/02 ,  H01L23/00 ,  H01L23/528 ,  H03K17/60

Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

公开(公告)号：US20250022873A1

公开(公告)日：2025-01-16

申请号：US18901620

申请日：2024-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masayuki AOIKE ,  Shinnosuke TAKAHASHI ,  Masatoshi HASE ,  Fumio HARIMA

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/14 ,  H01L23/373 ,  H01L23/528 ,  H01L29/205 ,  H01L29/737

Abstract: A bonding layer including a first metal region is disposed on at least a portion of an upper surface of a support substrate. An underlying layer including a sub-collector region that is made of a conductive semiconductor material and is electrically connected to the first metal region is disposed on the bonding layer. A first transistor including a collector layer electrically connected to the sub-collector region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer is disposed on the sub-collector region. On the sub-collector region, a collector electrode electrically connected to the sub-collector region is located outward of the first transistor to overlap the first metal region in plan view.

公开(公告)号：US20250007473A1

公开(公告)日：2025-01-02

申请号：US18883118

申请日：2024-09-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki TSUTSUI ,  Shinnosuke TAKAHASHI

IPC: H03F3/24 ,  H03F1/56

Abstract: A substrate ground conductor made of a semiconductor is provided. A transistor is configured with a collector layer, a base layer, and an emitter layer laminated on a substrate. A clamp circuit is configured with a plurality of elements disposed on the substrate. The clamp circuit is connected between the collector layer and the ground conductor or between the base layer and the ground conductor. The plurality of elements of the clamp circuit include a diode circuit made of a plurality of diodes, and a resistance element connected in series to the diode circuit. The resistance element is configured with a part of an epitaxial layer formed on the substrate.

公开(公告)号：US20240321975A1

公开(公告)日：2024-09-26

申请号：US18734477

申请日：2024-06-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Koji INOUE ,  Shinnosuke TAKAHASHI ,  Satoshi GOTO ,  Masao KONDO

IPC: H01L29/417 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L27/082 ,  H01L29/205 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/13 ,  H01L27/0823 ,  H01L29/205 ,  H01L29/7371 ,  H01L2224/13026 ,  H01L2924/10329 ,  H01L2924/10338 ,  H01L2924/13051

Abstract: A mesa structure including a collector layer, a base layer, and an emitter layer laminated on a substrate is formed. An emitter electrode electrically connected to the emitter layer is disposed on the mesa structure. Moreover, a base electrode electrically connected to the base layer is disposed on the mesa structure. A collector electrode is disposed in such a manner as to surround the mesa structure in plan view, and the collector electrode is electrically connected to the collector layer. The emitter electrode includes a first part and a second part. In plan view, the base electrode surrounds the first part of the emitter electrode, and the second part of the emitter electrode surrounds the base electrode.

公开(公告)号：US20220173702A1

公开(公告)日：2022-06-02

申请号：US17506752

申请日：2021-10-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Yasunari UMEMOTO ,  Shaojun MA ,  Shinnosuke TAKAHASHI

IPC: H03F1/30 ,  H03F3/24

Abstract: A power amplifier circuit includes an amplification unit, a heating unit, and a control circuit. The amplification unit is configured to amplify a radio-frequency signal. The heating unit is provided adjacent to the amplification unit. The heating unit includes one or more transistors configured to generate heat that increases as the passing current increases. The control circuit is coupled to the one or more transistors. The control circuit is configured to increase the passing current when the environmental temperature is a predetermined threshold or lower.

公开(公告)号：US20200303372A1

公开(公告)日：2020-09-24

申请号：US16820441

申请日：2020-03-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Masao KONDO ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI ,  Yasunari UMEMOTO ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H01L27/082 ,  H03F3/195 ,  H03F3/213 ,  H01L29/737

Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.