公开(公告)号：US20210327775A1

公开(公告)日：2021-10-21

申请号：US17224784

申请日：2021-04-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yoshimitsu TAKENOUCHI ,  Kenji SASAKI ,  Masao KONDO

IPC: H01L23/13 ,  H05K1/02 ,  H01L23/00

Abstract: An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.

公开(公告)号：US20180358933A1

公开(公告)日：2018-12-13

申请号：US16002457

申请日：2018-06-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toshiki MATSUI ,  Kenji SASAKI ,  Fumio HARIMA

IPC: H03F1/30 ,  H03F1/02 ,  H03F3/21 ,  H03F3/19 ,  H01L29/73 ,  H01L29/737

CPC classification number: H03F1/302 ,  H01L27/0772 ,  H01L29/41708 ,  H01L29/7304 ,  H01L29/7371 ,  H03F1/0205 ,  H03F1/0277 ,  H03F1/30 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/21 ,  H03F2200/408 ,  H03F2200/447 ,  H03F2200/451

Abstract: A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.

公开(公告)号：US20170186671A1

公开(公告)日：2017-06-29

申请号：US15454434

申请日：2017-03-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI

IPC: H01L23/482 ,  H01L29/04 ,  H01L29/08 ,  H01L21/306 ,  H01L29/205 ,  H01L27/082 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10

CPC classification number: H01L23/4824 ,  H01L21/30612 ,  H01L23/535 ,  H01L23/66 ,  H01L25/0655 ,  H01L25/16 ,  H01L27/0605 ,  H01L27/0823 ,  H01L29/045 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371 ,  H01L2223/6655 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/1305 ,  H01L2924/00

Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.

公开(公告)号：US20160155830A1

公开(公告)日：2016-06-02

申请号：US14932497

申请日：2015-11-04

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Kenji SASAKI ,  Kingo KUROTANI ,  Takashi KITAHARA

IPC: H01L29/737 ,  H03F3/21 ,  H03F3/19 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L29/7371 ,  H01L23/4824 ,  H01L23/535 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L27/0823 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/41708 ,  H01L2224/0401 ,  H01L2224/13013 ,  H01L2224/1302 ,  H01L2224/16227 ,  H01L2924/13051 ,  H03F3/19 ,  H03F2200/408 ,  H03F2200/451 ,  H01L2924/00012

Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

Abstract translation: 复合半导体器件包括异质结双极晶体管和凸块。 异质结双极晶体管包括多个单位晶体管。 凸块电连接到多个单位晶体管的发射极。 多个单位晶体管沿第一方向布置。 所述突起设置在所述多个单位晶体管的发射极之上，同时在所述第一方向上延伸。 多个单位晶体管中的至少一个的发射极从第一方向上的凸块的中心线向垂直于第一方向的第二方向的第一侧移位。 所述多个单位晶体管中的至少另一个的发射极在所述第一方向上朝向所述第二方向的第二侧从所述凸块的中心线偏移。

公开(公告)号：US20220093775A1

公开(公告)日：2022-03-24

申请号：US17399907

申请日：2021-08-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/205 ,  H01L29/08

Abstract: At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.

公开(公告)号：US20210305949A1

公开(公告)日：2021-09-30

申请号：US17216404

申请日：2021-03-29

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shaojun MA ,  Yasunari UMEMOTO ,  Kenji SASAKI

IPC: H03F3/21 ,  H01L27/06 ,  H01L49/02 ,  H01L29/205 ,  H01L29/737 ,  H01L23/66

Abstract: Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.

公开(公告)号：US20200091874A1

公开(公告)日：2020-03-19

申请号：US16569271

申请日：2019-09-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H03F3/19 ,  H03F3/213 ,  H03F1/30

Abstract: In a radio frequency power amplifier, a semiconductor chip includes at least one first transistor amplifying a radio frequency signal, a first external-connection conductive member connected to the first transistor, a bias circuit including a second transistor that applies a bias voltage to the first transistor, and a second external-connection conductive member connected to the second transistor. The second external-connection conductive member at least partially overlaps with the second transistor when viewed in plan.

公开(公告)号：US20190115338A1

公开(公告)日：2019-04-18

申请号：US16219886

申请日：2018-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Takayuki TSUTSUI ,  Isao OBU ,  Yasuhisa YAMAMOTO

IPC: H01L27/02 ,  H03F3/213 ,  H01L23/00 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H03F1/52 ,  H03F3/195

Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

公开(公告)号：US20190051645A1

公开(公告)日：2019-02-14

申请号：US16038040

申请日：2018-07-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Isao OBU

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/47

Abstract: A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer.

公开(公告)号：US20180262167A1

公开(公告)日：2018-09-13

申请号：US15976734

申请日：2018-05-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Kenichi SHIMAMOTO

IPC: H03F1/30 ,  H01L23/00 ,  H01L27/02 ,  H01L27/082 ,  H01L23/367 ,  H03F3/193 ,  H03F3/21

CPC classification number: H03F1/301 ,  H01L23/367 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L27/0248 ,  H01L27/082 ,  H01L2224/13013 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17519 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/451 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.