公开(公告)号：US20240204087A1

公开(公告)日：2024-06-20

申请号：US18593387

申请日：2024-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7371 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/0692 ,  H01L29/0817

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US20220060158A1

公开(公告)日：2022-02-24

申请号：US17453962

申请日：2021-11-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yasunari UMEMOTO ,  Yuichi SAITO ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H03F3/21 ,  H01F17/00 ,  H01L23/00 ,  H01L23/552 ,  H03F3/213 ,  H03F1/02 ,  H01L23/66 ,  H01L23/498

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

公开(公告)号：US20210083080A1

公开(公告)日：2021-03-18

申请号：US17002618

申请日：2020-08-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji SASAKI ,  Yasunari UMEMOTO ,  Shigeki KOYA ,  Shinnosuke TAKAHASHI ,  Masao KONDO

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L27/02 ,  H01L23/00 ,  H01L23/528 ,  H03K17/60

Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

公开(公告)号：US20160133732A1

公开(公告)日：2016-05-12

申请号：US14988016

申请日：2016-01-05

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/122 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/6631

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.

Abstract translation: 在双极晶体管中，集电极层包括三个半导体层：n型GaAs层（Si浓度：约5×10 15 cm -3，厚度：约350nm），p型GaAs层（C浓度：约4.5 ×1015cm-3，厚度：约100nm，片材浓度：4.5×10 10 cm -2），n型GaAs层Si浓度约5×10 15 cm -3，厚度约500nm。 p型GaAs层的片材浓度设定为小于1×1011cm-2。

公开(公告)号：US20160005841A1

公开(公告)日：2016-01-07

申请号：US14848090

申请日：2015-09-08

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Atsushi KUROKAWA

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08

CPC classification number: H01L29/7378 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66318 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor includes a collector layer composed of a semiconductor containing GaAs as a main component; a base layer including a first base layer and a second base layer the first base layer forming a heterojunction with the collector layer and being composed of a semiconductor containing a material as a main component, the material being lattice-mismatched to the main component of the collector layer, the first base layer having a film thickness less than a critical thickness at which a misfit dislocation is introduced, the second base layer being joined to the first base layer and composed of a semiconductor containing a material as a main component, and the material being lattice-matched to the main component of the collector layer; and an emitter layer that forms a heterojunction with the second base layer.

Abstract translation: 异质结双极晶体管包括由包含GaAs作为主要成分的半导体构成的集电极层; 基底层，包括第一基底层和第二基底层，所述第一基底层与所述集电体层形成异质结，并且由包含材料作为主要成分的半导体构成，所述材料与所述第一基底层的主要成分晶格错配 所述第一基底层的膜厚小于引入失配位错的临界厚度，所述第二基底层被接合到所述第一基底层并且由包含材料作为主要成分的半导体构成， 材料与集电极层的主要成分晶格匹配; 以及与第二基极层形成异质结的发射极层。

公开(公告)号：US20220029004A1

公开(公告)日：2022-01-27

申请号：US17495588

申请日：2021-10-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Shigeki KOYA ,  Masao KONDO ,  Takayuki TSUTSUI

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/308 ,  H01L29/66 ,  H03F3/213 ,  H03F3/195 ,  H01L29/205 ,  H03F3/21 ,  H03F1/56 ,  H03F3/24 ,  H01L23/00

Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

公开(公告)号：US20210257973A1

公开(公告)日：2021-08-19

申请号：US17168904

申请日：2021-02-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shaojun MA ,  Shigeki KOYA

IPC: H03F1/30 ,  H03F3/19 ,  H03F3/21

Abstract: A first amplifier circuit in a preceding stage, a second amplifier circuit in a subsequent stage, and a ground external connection terminal are disposed on a substrate. The first and second amplifier circuits each include bipolar transistors, capacitive elements for the respective bipolar transistors, and resistive elements for the respective bipolar transistors. The bipolar transistors each include separate base electrodes, that is, a first base electrode for radio frequency and a second base electrode for biasing. The bipolar transistors of the second amplifier circuit include emitter electrodes connected to the ground external connection terminal. The minimum spacing between the first base electrode and an emitter mesa layer of at least one of the bipolar transistors of the second amplifier circuit is greater than the minimum spacing between the first base electrode and am emitter mesa layer of each of the bipolar transistors of the first amplifier circuit.

公开(公告)号：US20210183854A1

公开(公告)日：2021-06-17

申请号：US17188961

申请日：2021-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Shigeki KOYA ,  Yasunari UMEMOTO ,  Takayuki TSUTSUI

IPC: H01L27/082 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498 ,  H01L21/8252

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

公开(公告)号：US20210091215A1

公开(公告)日：2021-03-25

申请号：US17109897

申请日：2020-12-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Isao OBU

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US20210044256A1

公开(公告)日：2021-02-11

申请号：US17082990

申请日：2020-10-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Takayuki TSUTSUI ,  Yasunari UMEMOTO ,  Isao OBU ,  Satoshi TANAKA

IPC: H03F1/32 ,  H03G3/00 ,  H03F1/02 ,  H03F1/56 ,  H03F3/24 ,  H03F3/19 ,  H03F3/21 ,  H03G3/30

Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.