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    MULTILAYER CAPACITOR
    11.
    发明申请
    MULTILAYER CAPACITOR 审中-公开
    多层电容器

    公开(公告)号：US20160240314A1

    公开(公告)日：2016-08-18

    申请号：US15014161

    申请日：2016-02-03

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII

    IPC: H01G4/228 ,  H01G4/012 ,  H01G4/224 ,  H01G4/30

    CPC classification number: H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H05K3/3442 ,  H05K2201/10015

    Abstract: A multilayer ceramic capacitor includes a capacitor body and first to fourth outer connectors. The capacitor body includes dielectric layers and conductor layers, first and second principal surfaces facing each other in a height direction, first and second side surfaces facing each other in a length direction, and third and fourth side surfaces facing each other in a width direction. The first to fourth outer connectors cover portions of the first to fourth side surfaces, respectively. In a case where L0, W0, and H0 are maximum external dimensions of the multilayer ceramic capacitor in the length direction, the width direction, and the height direction, respectively, L0, W0, and H0 satisfy a condition of about 2.67≦L0/H0 and a condition of about 1/1.72≦L0/W0≦about 1.72.

    Abstract translation: 多层陶瓷电容器包括电容器本体和第一至第四外部连接器。 电容器本体包括电介质层和导体层，第一和第二主表面在高度方向上彼此面对，在长度方向上彼此面对的第一和第二侧表面以及在宽度方向上彼此面对的第三和第四侧表面。 第一至第四外部连接器分别覆盖第一至第四侧面的部分。 在L0，W0和H0分别是多层陶瓷电容器在长度方向，宽度方向和高度方向上的最大外部尺寸L0，W0和H0满足条件约2.67≤L0/ H0和大约1 /1.72≤L0/W0≤约1.72的条件。

    MULTILAYER CAPACITOR, TAPING MULTILAYER CAPACITOR SERIES, AND MOUNTING STRUCTURE OF MULTILAYER CAPACITOR
    12.
    发明申请
    MULTILAYER CAPACITOR, TAPING MULTILAYER CAPACITOR SERIES, AND MOUNTING STRUCTURE OF MULTILAYER CAPACITOR 有权
    多层电容器，多层电容器系列和多层电容器的安装结构

    公开(公告)号：US20140211368A1

    公开(公告)日：2014-07-31

    申请号：US14148992

    申请日：2014-01-07

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII

    IPC: H01G4/30

    CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12

    Abstract: A multilayer capacitor that achieves reduced acoustic noise includes a capacitor body including a capacitance generating portion, a first outer layer portion, and a second outer layer portion. First and second internal electrodes are provided in the capacitance generating portion. The first outer layer portion is located between the capacitance generating portion and a first principle surface. The second outer layer portion is located between the capacitance generating portion and a second principle surface. The second outer layer portion is thicker than the first outer layer portion. At least one of a concave portion and a convex portion is provided on the second principle surface.

    Abstract translation: 实现降低的声学噪声的层叠电容器包括：电容器体，包括电容产生部，第一外层部和第二外层部。 第一和第二内部电极设置在电容产生部分中。 第一外层部分位于电容产生部分和第一原理表面之间。 第二外层部分位于电容产生部分和第二主表面之间。 第二外层部分比第一外层部分厚。 凹部和凸部中的至少一个设置在第二原理面上。

    MONOLITHIC CAPACITOR
    13.
    发明申请
    MONOLITHIC CAPACITOR 有权
    单片电容器

    公开(公告)号：US20140153155A1

    公开(公告)日：2014-06-05

    申请号：US13914957

    申请日：2013-06-11

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII ,  Yoshinao NISHIOKA

    IPC: H01G4/30 ,  H01G4/01

    CPC classification number: H01G4/01 ,  H01G4/012 ,  H01G4/302

    Abstract: A monolithic capacitor includes a laminated body including stacked dielectric layers and substantially in the shape of a rectangular parallelepiped, and including a first surface being a mounting surface, a second surface opposite to the first surface, opposing third and fourth surfaces orthogonal to the first and second surfaces, and opposing fifth and sixth surfaces orthogonal to the first to fourth surfaces; capacitor electrodes disposed in the laminated body and each including a capacitive portion and a lead portion extending therefrom to at least one surface of the laminated body, the capacitive portions facing each other with dielectric layers interposed therebetween; and first and second outer electrodes disposed on at least one surface of the laminated body and connected to the lead portions. A gap between the first surface and the capacitive portions is greater than a gap between the second surface and the capacitive portions.

    Abstract translation: 单片电容器包括层叠体，该层叠体包括堆积的电介质层，并且基本上呈长方体形状，并且包括第一表面，即第一表面，与第一表面相对的第二表面，与第一表面正交的相对的第三和第四表面， 第二表面和与第一至第四表面正交的相对的第五和第六表面; 电容电极设置在所述层叠体中，并且每个电容电极包括电容部分和从其延伸到所述层叠体的至少一个表面的引线部分，所述电容部分彼此面对，其间插入介电层; 以及设置在所述层叠体的至少一个表面上并连接到所述引线部分的第一和第二外部电极。 第一表面和电容部分之间的间隙大于第二表面和电容部分之间的间隙。

    ELECTRONIC COMPONENT
    14.
    发明申请
    ELECTRONIC COMPONENT 有权
    电子元件

    公开(公告)号：US20140008116A1

    公开(公告)日：2014-01-09

    申请号：US14027403

    申请日：2013-09-16

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII ,  Yoshinao NISHIOKA

    IPC: H05K1/02 ,  H05K1/16

    CPC classification number: H05K1/0216 ,  H05K1/111 ,  H05K1/16 ,  H05K3/3442 ,  H05K2201/2045 ,  Y02P70/611

    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.

    Abstract translation: 安装结构包括安装在电路板上的电子部件。 接地电极设置在电路板主体上，并分别通过焊料与电子部件的外部电极连接。 从每个焊盘电极到对应焊料的顶部的距离不大于从每个焊盘电极到暴露在电子部件的端面处的电容器导体的暴露部分的距离的大约1.27倍，电容器 导体定位成最靠近电路板。

    ELECTRONIC COMPONENT
    15.
    发明申请
    ELECTRONIC COMPONENT 有权
    电子元件

    公开(公告)号：US20130233606A1

    公开(公告)日：2013-09-12

    申请号：US13873303

    申请日：2013-04-30

    Applicant: MURATA MANUFACTURING CO., LTD.

    Inventor： Yasuo FUJII ,  Yoshinao NISHIOKA

    IPC: H05K1/02 ,  H05K1/16

    CPC classification number: H05K1/0216 ,  H05K1/111 ,  H05K1/16 ,  H05K3/3442 ,  H05K2201/2045 ,  Y02P70/611

    Abstract: A mounting structure includes an electronic component mounted on a circuit board. Land electrodes are disposed on a board body and are connected to outer electrodes of the electronic component through solders, respectively. A distance from each of the land electrodes to a top of the corresponding solder is not larger than about 1.27 times a distance from each of the land electrodes to an exposed portion of a capacitor conductor exposed at an end surface of the electronic component, the capacitor conductor being positioned closest to the circuit board.

    Abstract translation: 安装结构包括安装在电路板上的电子部件。 接地电极设置在电路板主体上，并分别通过焊料与电子部件的外部电极连接。 从每个焊盘电极到对应焊料的顶部的距离不大于从每个焊盘电极到暴露在电子部件的端面处的电容器导体的暴露部分的距离的大约1.27倍，电容器 导体定位成最靠近电路板。

    MULTILAYER CERAMIC ELECTRONIC COMPONENT
    18.
    发明申请
    MULTILAYER CERAMIC ELECTRONIC COMPONENT 审中-公开

    公开(公告)号：US20170352487A1

    公开(公告)日：2017-12-07

    申请号：US15611887

    申请日：2017-06-02

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Takayuki KAYATANI ,  Takashi SAWADA ,  Yasuo FUJII

    IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12 ,  H01G4/228 ,  H01G4/224

    CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1227 ,  H01G4/1236 ,  H01G4/224 ,  H01G4/228 ,  H01G4/232

    Abstract: A multilayer ceramic electronic component includes a laminated body, a first external electrode, a pair of second external electrodes, and a pair of insulating coating portions. The pair of insulating coating portions extends in a laminating direction between each of the pair of second external electrodes and the first external electrode on a second principal surface, from the second principal surface to respective portions of a first side surface and a second side surface. A maximum thickness of the first external electrode on the second principal surface is larger than a maximum thickness of the pair of second external electrodes on the second principal surface. The maximum thickness of the pair of second external electrodes on the second principal surface is larger than a maximum thickness of the pair of insulating coating portions on the second principal surface.

    ANALYSIS DEVICE AND ANALYSIS METHOD
    20.
    发明申请
    ANALYSIS DEVICE AND ANALYSIS METHOD 审中-公开
    分析装置和分析方法

    公开(公告)号：US20160011040A1

    公开(公告)日：2016-01-14

    申请号：US14865584

    申请日：2015-09-25

    Applicant: MURATA MANUFACTURING CO., LTD.

    Inventor： Hiroshi MIFUNE ,  Seiji HIDAKA ,  Yasuo FUJII

    IPC: G01H17/00

    CPC classification number: G01H17/00 ,  G01H1/00 ,  G01H11/08 ,  G06F17/5018

    Abstract: An analysis device constructs an analytical model with a circuit board and a medium, and applies a concentrated load grouping composed of concentrated loads to the circuit board. In this case, the concentrated loads are established such that the sum of the respective vectors is zero, and such that the torque is zero with respect to the center of gravity. The analysis device applies a finite element method to the analytical model to figure out the vibration of the circuit board, which is caused when the concentrated loads vibrate with a constant period. The change in the pressure of the medium is computed from the vibration of the circuit board, and the change in the pressure is converted to a sound pressure.

    Abstract translation: 分析装置使用电路板和介质构建分析模型，并将由集中负载组成的集中负载分组应用于电路板。 在这种情况下，集中的负载被建立为使得各个矢量的和为零，并且使得转矩相对于重心为零。 分析装置对分析模型应用有限元法，计算出集中负荷在恒定周期内振动时引起的电路板振动。 根据电路板的振动计算介质的压力变化，并将压力变化转换为声压。

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