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    VOLTAGE SMOOTHING CIRCUIT, VOLTAGE CONVERSION CIRCUIT, AND METHOD FOR CONTROLLING VOLTAGE TO BE APPLIED TO MULTILAYER CAPACITOR
    4.
    发明申请
    VOLTAGE SMOOTHING CIRCUIT, VOLTAGE CONVERSION CIRCUIT, AND METHOD FOR CONTROLLING VOLTAGE TO BE APPLIED TO MULTILAYER CAPACITOR 有权
    电压平滑电路，电压转换电路和控制电压应用于多层电容器的方法

    公开(公告)号：US20150325376A1

    公开(公告)日：2015-11-12

    申请号：US14701756

    申请日：2015-05-01

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII

    IPC: H01G4/30 ,  H02M5/42 ,  H01G2/06 ,  H01G4/248 ,  H01G4/38

    CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/248 ,  H01G4/30 ,  H02M1/15 ,  H02M3/07 ,  H02M5/42

    Abstract: A voltage smoothing circuit includes a first multilayer capacitor, a second multilayer capacitor, and a regulator including an input terminal electrically connected to the second multilayer capacitor and an output terminal electrically connected to the first multilayer capacitor. The regulator calculates a first voltage applied to the first multilayer capacitor based on a second voltage applied to the second multilayer capacitor from the input terminal such that a potential difference which is applied to the first multilayer capacitor decreases or increases when a potential difference which is applied to the second multilayer capacitor increases or decreases, and outputs the first voltage from the output terminal.

    Abstract translation: 电压平滑电路包括第一层叠电容器，第二层叠电容器和包括电连接到第二层叠电容器的输入端子和与第一层叠电容器电连接的输出端子的调节器。 调节器基于从输入端子施加到第二层叠电容器的第二电压来计算施加到第一层叠电容器的第一电压，使得施加到第一层叠电容器的电位差在施加的电位差​​时减小或增加 向第二层叠电容器增加或减小，并从输出端子输出第一电压。

    ELECTRONIC COMPONENT
    5.
    发明申请
    ELECTRONIC COMPONENT 审中-公开

    公开(公告)号：US20170352479A1

    公开(公告)日：2017-12-07

    申请号：US15613491

    申请日：2017-06-05

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Takashi SAWADA ,  Yasuo FUJII ,  Takayuki KAYATANI

    IPC: H01G4/12 ,  H01G4/30 ,  H01G4/008

    CPC classification number: H01G4/1245 ,  H01G4/008 ,  H01G4/06 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30

    Abstract: An electronic component includes a multilayer body, first to fourth outer electrodes, a pair of first insulating coating portions, and a pair of second insulating coating portions. The pair of first insulating coating portions is in at least one of a state in which inner end portions are in contact with the third outer electrode and a state in which outer end portions are in contact with the first outer electrode and the second outer electrode. The pair of second insulating coating portions is in at least one of a state in which inner end portions are in contact with the fourth outer electrode and a state in which outer end portions are in contact with the first outer electrode and the second outer electrode.

    LAMINATED ELECTRONIC COMPONENT AND MOUNTING STRUCTURE THEREOF
    7.
    发明申请
    LAMINATED ELECTRONIC COMPONENT AND MOUNTING STRUCTURE THEREOF 审中-公开
    层压电子元件及其安装结构

    公开(公告)号：US20140284091A1

    公开(公告)日：2014-09-25

    申请号：US14202457

    申请日：2014-03-10

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII

    IPC: H01G2/02 ,  H01G4/12

    CPC classification number: H01G2/06 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/0311 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10962 ,  Y02P70/611

    Abstract: A laminated electronic component includes a laminate including internal electrodes and dielectric layers laminated alternately and a first main surface, an external electrode that continuously covers at least one end surface of the laminate in a longitudinal direction and a portion of the first main surface adjacent to the one end surface, and a conductive elastic structure connected to the external electrode at at least corner portions of the first main surface in a portion where the external electrode covers the first main surface. The elastic structure includes a base portion connected to the external electrode to extend along the first main surface, and a branch portion branched from the base portion and extending at a position spaced from the first main surface to connect to another electrode, and having elasticity.

    Abstract translation: 层叠电子部件包括层叠体，其包括交替层叠的内部电极和电介质层，以及第一主面，连续地覆盖层叠体的长度方向的至少一个端面的外部电极和与第一主表面相邻的部分的外部电极 一个端面，以及在外部电极覆盖第一主表面的部分中的至少在第一主表面的角部处连接到外部电极的导电弹性结构。 所述弹性结构包括与所述外部电极连接的基部，沿着所述第一主表面延伸，以及从所述基部分支并在与所述第一主表面间隔开的位置延伸以连接到另一电极并具有弹性的分支部。

    MULTILAYER CAPACITOR
    8.
    发明申请
    MULTILAYER CAPACITOR 审中-公开

    公开(公告)号：US20190131068A1

    公开(公告)日：2019-05-02

    申请号：US16233268

    申请日：2018-12-27

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuo FUJII

    IPC: H01G4/012 ,  H01G4/30 ,  H01G4/35 ,  H01G4/232

    CPC classification number: H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H05K3/3442 ,  H05K2201/10015

    Abstract: A multilayer ceramic capacitor includes a capacitor body and first to fourth outer connectors. The capacitor body includes dielectric layers and conductor layers, first and second principal surfaces facing each other in a height direction, first and second side surfaces facing each other in a length direction, and third and fourth side surfaces facing each other in a width direction. The first to fourth outer connectors cover portions of the first to fourth side surfaces, respectively. In a case where L0, W0, and H0 are maximum external dimensions of the multilayer ceramic capacitor in the length direction, the width direction, and the height direction, respectively, L0, W0, and H0 satisfy a condition of about 2.67≤L0/H0 and a condition of about 1/1.72≤L0/W0 ≤ about 1.72.

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