公开(公告)号：US07723193B2

公开(公告)日：2010-05-25

申请号：US12149329

申请日：2008-04-30

申请人： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

发明人： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC分类号： H01L21/336

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

摘要翻译： 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

公开(公告)号：US07385247B2

公开(公告)日：2008-06-10

申请号：US10986018

申请日：2004-11-12

申请人： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

发明人： Hwa-Sung Rhee ,  Hyun-Suk Kim ,  Ueno Tetsuji ,  Jae-Yoon Yoo ,  Seung-Hwan Lee ,  Ho Lee ,  Moon-han Park

IPC分类号： H01L29/78

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.

摘要翻译： 至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面 基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

公开(公告)号：US20070054457A1

公开(公告)日：2007-03-08

申请号：US11517246

申请日：2006-09-08

申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636

摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

摘要翻译： 示例实施例涉及制造半导体器件的方法。 其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。 提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。 制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域 通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及 在蚀刻的半导体衬底上原位形成外延区域。

公开(公告)号：US20050023646A1

公开(公告)日：2005-02-03

申请号：US10851336

申请日：2004-05-24

申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

摘要： A multi-layered structure of a semiconducotr device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

公开(公告)号：US07776723B2

公开(公告)日：2010-08-17

申请号：US11192085

申请日：2005-07-29

申请人： Ho Lee ,  DongSuk Shin ,  Tetsuji Ueno ,  Seung-Hwan Lee ,  Hwa-Sung Rhee

发明人： Ho Lee ,  DongSuk Shin ,  Tetsuji Ueno ,  Seung-Hwan Lee ,  Hwa-Sung Rhee

IPC分类号： H01L21/322

CPC分类号： H01L21/3221 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02573 ,  H01L21/0262 ,  H01L27/1463 ,  H01L27/14643 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.

摘要翻译： 在制造外延半导体衬底的方法的示例性实施例中，在半导体衬底上生长吸杂层。 然后可以在吸气层上形成外延层，并且可以在外延层上形成半导体器件。

公开(公告)号：US07601983B2

公开(公告)日：2009-10-13

申请号：US11207703

申请日：2005-08-19

申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

IPC分类号： H01L29/10

CPC分类号： H01L29/66636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

摘要翻译： 晶体管包括具有{100}晶面的第一表面，{100}晶面的第二表面的半导体衬底的高度低于第一表面的第一表面，以及{111}晶体的第三表面 将第一表面连接到第二表面的平面。 在第二表面下形成第一重掺杂杂质区。 栅极结构形成在第一表面上。 在第二表面和第三表面上形成外延层。 在栅极结构的两侧形成第二重掺杂杂质区。 第二重掺杂杂质区域具有{111}晶面的侧面，从而可以防止在杂质区域之间产生的短沟道效应。

公开(公告)号：US07101776B2

公开(公告)日：2006-09-05

申请号：US10806301

申请日：2004-03-22

申请人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

发明人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/44 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

摘要： There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

摘要翻译： 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

公开(公告)号：US20060038200A1

公开(公告)日：2006-02-23

申请号：US11204564

申请日：2005-08-15

申请人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

发明人： Ho Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Ueno Tetsuji ,  Seung-Hwan Lee

IPC分类号： H01L31/0328 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/26586 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7834

摘要： According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount of a strained silicon layer during semiconductor fabrication processes. To the end, at least one gate pattern is disposed on an active region of a semiconductor substrate. Reinforcement layer patterns are formed to extend respectively from sidewalls of the gate pattern and disposed on a main surface of the semiconductor substrate. Each reinforcement layer pattern partially exposes each sidewall of the gate pattern. Impurity regions are disposed in the reinforcement layer patterns and the active region of the semiconductor substrate and overlap the gate pattern. Spacer patterns are disposed on the reinforcement layer patterns and partially cover the sidewalls of the gate pattern.

摘要翻译： 根据本发明的一些实施例，提供了包括具有加强层图案的晶体管和其形成方法的线光掩模。 晶体管和方法提供了在半导体制造工艺期间补偿部分去除量的应变硅层的方法。 最后，在半导体衬底的有源区上设置至少一个栅极图案。 加强层图案分别形成为从栅极图案的侧壁延伸并设置在半导体衬底的主表面上。 每个加强层图案部分地暴露栅极图案的每个侧壁。 杂质区域设置在加强层图案和半导体衬底的有源区域中并与栅极图案重叠。 间隔图案设置在加强层图案上并且部分覆盖栅极图案的侧壁。

公开(公告)号：US20050274981A1

公开(公告)日：2005-12-15

申请号：US11194529

申请日：2005-08-02

申请人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

发明人： Ho Lee ,  Moon-Han Park ,  Hwa-Sung Rhee ,  Jae-Yoon Yoo ,  Seung-Hwan Lee

IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L31/072 ,  H01L31/117

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251

摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

摘要翻译： 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。 此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。 因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

公开(公告)号：US20050009265A1

公开(公告)日：2005-01-13

申请号：US10806301

申请日：2004-03-22

申请人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

发明人： Jae-Yoon Yoo ,  Hwa-Sung Rhee ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/84

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

摘要： There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.

摘要翻译： 提供了使用总栅极硅化工艺制造MOS晶体管的方法。 该方法包括在半导体衬底上形成绝缘栅极图案。 绝缘栅图案包括依次层叠的硅图案和牺牲层图案。 形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。 通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。 暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。