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    GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE
    12.
    发明申请
    GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE 有权
    接地参考单端信号连接图形处理单元多芯片模块

    公开(公告)号：US20140266417A1

    公开(公告)日：2014-09-18

    申请号：US13973947

    申请日：2013-08-22

    Applicant: NVIDIA Corporation

    Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

    IPC: H01L23/535

    CPC classification number: H01L23/535 ,  G06F13/00 ,  G06F13/4072 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H03K19/00 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

    Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，图形处理集群（GPC）芯片和被配置为包括第一处理器芯片，GPC芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 GPC芯片被配置为包括第二单端信令接口电路并执行着色器程序。 在MCM封装内制造的第二组电迹线，用于将第二单端信令接口电路耦合到互连电路。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

    Dual-trigger low-energy flip-flop circuit
    13.
    发明授权
    Dual-trigger low-energy flip-flop circuit 有权
    双触发低能触发电路

    公开(公告)号：US08604855B2

    公开(公告)日：2013-12-10

    申请号：US13921138

    申请日：2013-06-18

    Applicant: NVIDIA Corporation

    Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Ge Yang

    IPC: H03K3/356

    CPC classification number: H03K3/36 ,  H03K3/012 ,  H03K3/356121

    Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

    Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可以布防，并且在时钟的上升沿触发置位或复位。

    Generalized acceleration of matrix multiply accumulate operations
    14.
    发明授权
    Generalized acceleration of matrix multiply accumulate operations 有权

    公开(公告)号：US11797303B2

    公开(公告)日：2023-10-24

    申请号：US17351175

    申请日：2021-06-17

    Applicant: NVIDIA Corporation

    Inventor： Brent Ralph Boswell ,  Ming Y. Siu ,  Jack H. Choquette ,  Jonah M. Alben ,  Stuart Oberman

    IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

    CPC classification number: G06F9/30014 ,  G06F9/3001 ,  G06F9/3012 ,  G06F9/30036 ,  G06F9/3851 ,  G06T1/20

    Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

    Fault injection architecture for resilient GPU computing
    16.
    发明授权
    Fault injection architecture for resilient GPU computing 有权

    公开(公告)号：US10922203B1

    公开(公告)日：2021-02-16

    申请号：US16138747

    申请日：2018-09-21

    Applicant: NVIDIA Corporation

    Inventor： Jonah M. Alben ,  Sachin Satish Idgunji ,  Jue Wu

    IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G01R31/3177 ,  G06F1/12 ,  G06T1/20 ,  G06F1/10 ,  G11C11/409 ,  H03K3/037

    Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience. Normal processor execution is halted to inject a given state error through a scan chain, and execution is subsequently resumed.

    Generalized acceleration of matrix multiply accumulate operations
    17.
    发明授权
    Generalized acceleration of matrix multiply accumulate operations 有权

    公开(公告)号：US10884734B2

    公开(公告)日：2021-01-05

    申请号：US16459191

    申请日：2019-07-01

    Applicant: NVIDIA Corporation

    Inventor： Brent Ralph Boswell ,  Ming Y. Siu ,  Jack H. Choquette ,  Jonah M. Alben ,  Stuart Oberman

    IPC: G06F9/30 ,  G06T1/20 ,  G06F9/38

    Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

    GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS
    18.
    发明申请
    GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS 审中-公开

    公开(公告)号：US20180321938A1

    公开(公告)日：2018-11-08

    申请号：US15826435

    申请日：2017-11-29

    Applicant: NVIDIA Corporation

    Inventor： Brent Ralph Boswell ,  Ming Y. Siu ,  Jack H. Choquette ,  Jonah M. Alben ,  Stuart Oberman

    IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20

    CPC classification number: G06F9/30014 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/3851 ,  G06T1/20

    Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

    Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
    20.
    发明授权
    Ground-referenced single-ended signaling connected graphics processing unit multi-chip module 有权
    接地参考单端信号连接图形处理单元多芯片模块

    公开(公告)号：US09153539B2

    公开(公告)日：2015-10-06

    申请号：US13973947

    申请日：2013-08-22

    Applicant: NVIDIA Corporation

    Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

    IPC: G11C11/40 ,  H01L23/535 ,  G06F13/00 ,  H03K19/00

    CPC classification number: H01L23/535 ,  G06F13/00 ,  G06F13/4072 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/15311 ,  H03K19/00 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2924/00

    Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a graphics processing cluster (GPC) chip, and an MCM package configured to include the first processor chip, the GPC chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The GPC chip is configured to include a second single-ended signaling interface circuit and to execute shader programs. A second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling interface circuit to the interconnect circuit. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

    Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，图形处理集群（GPC）芯片和被配置为包括第一处理器芯片，GPC芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 GPC芯片被配置为包括第二单端信令接口电路并执行着色器程序。 在MCM封装内制造的第二组电迹线，用于将第二单端信令接口电路耦合到互连电路。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

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