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公开(公告)号：US20140132245A1
公开(公告)日：2014-05-15
申请号：US13676021
申请日：2012-11-13
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally , Stephen G. Tell
IPC: G01R25/00
CPC classification number: G01R25/00
Abstract: A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.
Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 产生一组第一时钟信号的延迟版本。 第一时钟的延迟版本集用于采样第二时钟信号，产生与第一时钟信号相对应的域中的采样序列。 至少一个边缘指示位于样本序列内。
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公开(公告)号：US20230387922A1
公开(公告)日：2023-11-30
申请号：US18106398
申请日：2023-02-06
Applicant: NVIDIA Corporation
Inventor： Sanquan Song , Stephen G. Tell , Nikola Nedovic
CPC classification number: H03L7/099 , H03L7/0891
Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.
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公开(公告)号：US20190068203A1
公开(公告)日：2019-02-28
申请号：US15693325
申请日：2017-08-31
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
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14.发明授权System and method for determining a time for safely sampling a signal of a clock domain 有权用于确定用于安全采样时钟域的信号的时间的系统和方法公开(公告)号：US08879681B2
公开(公告)日：2014-11-04
申请号：US13849414
申请日：2013-03-22
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Stephen G. Tell
CPC classification number: H04L7/033 , H04L7/0012 , H04L7/005
Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.
Abstract translation: 提供了一种系统和方法，用于确定用于对码区域的信号进行安全采样的时间。 在一个实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用频率估计被第二时钟域安全地采样。 在另一实施例中，使用频率估计器来计算第一对接域的频率估计。 此外，利用相位估计器，基于频率估计来计算第一时钟域的相位估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用相位估计被第二时钟域安全地采样。
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公开(公告)号：US20140149780A1
公开(公告)日：2014-05-29
申请号：US13688170
申请日：2012-11-28
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally , Stephen G. Tell
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.
Abstract translation: 提供了一种用于推测周期性同步的方法和系统。 接收表示相对于在至少一个周期测量的第一时钟信号的第二时钟信号的测量相位的相位值。 还接收表示相对于先前测量的至少一个周期的第一时钟信号的第二时钟信号的周期的周期值。 基于相位值和周期值确定缩短的定时裕度。 基于减小的时序余量产生推测同步的输出信号。
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Patent Agency Ranking
16.发明申请公开(公告)号：US20130216013A1
公开(公告)日：2013-08-22
申请号：US13849414
申请日：2013-03-22
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally , Stephen G. Tell
IPC: H04L7/033
CPC classification number: H04L7/033 , H04L7/0012 , H04L7/005
Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.
Abstract translation: 提供了一种系统和方法，用于确定用于对码区域的信号进行安全采样的时间。 在一个实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用频率估计由第二时钟域安全地采样。 在另一实施例中，使用频率估计器来计算第一对接域的频率估计。 此外，利用相位估计器，基于频率估计来计算第一时钟域的相位估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用相位估计被第二时钟域安全地采样。
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17.发明申请公开(公告)号：US20130070880A1
公开(公告)日：2013-03-21
申请号：US13674864
申请日：2012-11-12
Applicant: NVIDIA Corporation
Inventor： Stephen G. Tell
IPC: H04L7/00
CPC classification number: H04L7/0012 , G06F5/10 , G06F7/49989 , G06F2205/106 , H04L7/005
Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.
Abstract translation: 提供了一种用于确定对时钟域的信号进行安全采样的时间的系统和方法。 在一个实施例中，基于第二时钟域和第一时钟域之间的相对频率估计，并且基于相位估计，计算来自第一时钟域的信号的第一时间，第一时钟域的相位估计 是不变的，使得能够被第二时钟域安全采样的信号被确定为在第二时钟域中产生第一采样信号。 另外，计算更新的相位估计，并且基于更新的相位估计，确定来自第一时钟域的信号改变的第二时间，使得信号不能被第二时钟域安全地采样 。 在第二时间期间，维持第二时钟域中的第一采样信号。
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公开(公告)号：US12033060B2
公开(公告)日：2024-07-09
申请号：US16750917
申请日：2020-01-23
Applicant: NVIDIA Corporation
Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.
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公开(公告)号：US11962312B2
公开(公告)日：2024-04-16
申请号：US18106398
申请日：2023-02-06
Applicant: NVIDIA Corporation
Inventor： Sanquan Song , Stephen G. Tell , Nikola Nedovic
CPC classification number: H03L7/099 , H03L7/0891
Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.
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公开(公告)号：US10601409B2
公开(公告)日：2020-03-24
申请号：US15693325
申请日：2017-08-31
Applicant: NVIDIA Corporation
Inventor： John W. Poulton , Sudhir Shrikantha Kudva , Stephen G. Tell , John Michael Wilson
IPC: H03K3/356 , H03K5/135 , H03K19/096 , H02M3/156 , G05F1/575
Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.
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