Doherty amplifier circuits
    11.
    发明授权

    公开(公告)号:US10050588B2

    公开(公告)日:2018-08-14

    申请号:US15596416

    申请日:2017-05-16

    Applicant: NXP B.V.

    Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

    Metal oxide semiconductor device
    12.
    发明授权

    公开(公告)号:US12211840B2

    公开(公告)日:2025-01-28

    申请号:US17644138

    申请日:2021-12-14

    Applicant: NXP B.V.

    Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, (470) are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL (470) are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction (602) and a second direction (604) that is orthogonal to the first direction (602); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (606), where the third direction (606) is orthogonal to both the first direction (602) and the second direction (604).

    ANTENNA SWITCH CIRCUIT AND METHOD
    13.
    发明申请

    公开(公告)号:US20220352908A1

    公开(公告)日:2022-11-03

    申请号:US17660392

    申请日:2022-04-22

    Applicant: NXP B.V.

    Abstract: An antenna switch circuit and an antenna circuit switching method. The circuit includes an antenna port, a termination port (e.g., for disposal of power reflected back from an antenna and received through the antenna port in a transmit mode), and a receive port (e.g., for receiving a signal from the antenna port via the antenna switch circuit in a receive mode). The circuit also includes a first switch coupled between the antenna port and the termination port. The circuit further includes a resonant inductance coupled between the receive port and the node located between the antenna port and the first switch. The circuit also includes a second switch coupled between a reference potential and a node located between the resonant inductance and the receive port.

    Power amplifier
    14.
    发明授权

    公开(公告)号:US10826446B2

    公开(公告)日:2020-11-03

    申请号:US16354277

    申请日:2019-03-15

    Applicant: NXP B.V.

    Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

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