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公开(公告)号：US20200274575A1
公开(公告)日：2020-08-27
申请号：US16794846
申请日：2020-02-19
Applicant: NXP B.V.
Inventor： Xin Yang , Mark Pieter van der Heijden , Gerben Willem de Jong
IPC: H04B1/44 , H03H11/28 , H03K17/567 , H04L5/16
Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided,
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公开(公告)号：US20180006611A1
公开(公告)日：2018-01-04
申请号：US15596416
申请日：2017-05-16
Applicant: NXP B.V.
Inventor： Gerben Willem de Jong , Mark Pieter van der Heijden , Jozef Reinerus Maria Bergervoet , Tony Vanhoucke , Gian Hoogzaad , Ivan Matkov Zahariev
CPC classification number: H03F1/0288 , H01L23/66 , H03F1/30 , H03F1/56 , H03F1/565 , H03F3/195 , H03F3/213 , H03F2200/211 , H03F2200/213 , H03F2200/216 , H03F2200/318 , H03F2200/387 , H03F2200/391 , H03F2200/408 , H03F2200/447 , H03F2200/468 , H03F2200/534 , H03F2200/541 , H04L65/1036 , H04L65/1069 , H04L65/80
Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.
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公开(公告)号：US10090295B2
公开(公告)日：2018-10-02
申请号：US15619694
申请日：2017-06-12
Applicant: NXP B.V.
IPC: H03F3/04 , H01L27/06 , H03K19/088 , G11C11/412 , H03K3/356
Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
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公开(公告)号：US20230170853A1
公开(公告)日：2023-06-01
申请号：US18052992
申请日：2022-11-07
Applicant: NXP B.V.
Inventor： Gian Hoogzaad , Gerben Willem de Jong , Robert Victor Buytenhuijs
CPC classification number: H03F1/565 , H03F1/523 , H03F1/226 , H03F3/165 , H03F2200/462
Abstract: A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.
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Patent Agency Ranking
公开(公告)号：US11482974B2
公开(公告)日：2022-10-25
申请号：US17027782
申请日：2020-09-22
Applicant: NXP B.V.
Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
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公开(公告)号：US20180006021A1
公开(公告)日：2018-01-04
申请号：US15619694
申请日：2017-06-12
Applicant: NXP B.V.
IPC: H01L27/06 , G11C11/412 , H03K3/356 , H03K19/088
CPC classification number: H01L27/0652 , G11C11/412 , H03F1/0288 , H03F1/52 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/18 , H03F2200/21 , H03F2200/411 , H03F2200/42 , H03F2200/432 , H03F2200/444 , H03F2200/451 , H03F2200/555 , H03F2200/75 , H03K3/356 , H03K3/356104 , H03K19/088
Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
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公开(公告)号：US20210126597A1
公开(公告)日：2021-04-29
申请号：US17027782
申请日：2020-09-22
Applicant: NXP B.V.
Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
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公开(公告)号：US10985795B2
公开(公告)日：2021-04-20
申请号：US16794846
申请日：2020-02-19
Applicant: NXP B.V.
Inventor： Xin Yang , Mark Pieter van der Heijden , Gerben Willem de Jong
IPC: H04B1/44 , H03H11/28 , H03K17/567 , H04L5/16
Abstract: A switch arrangement comprising: a transceiver node coupled to a first and second circuit branch, the first circuit branch including a transmit node, the second circuit branch including a receive node; wherein the first circuit branch comprises an inductor coupled in series and a first semiconductor switch, in parallel, configured to provide a switched coupling to a reference voltage; and wherein the second circuit branch comprises one of: i) a second and third semiconductor switch; and ii) a second semiconductor switch and a third semiconductor switch configured to control the application of a supply voltage to an amplifier; and iii) a further semiconductor switch configured to control the application of a bias current to an amplifier; wherein in the first switch mode, impedance matching between the transceiver node and transmit node is provided; in the second switch mode, impedance matching between the transceiver node and receive node is provided.
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公开(公告)号：US10050588B2
公开(公告)日：2018-08-14
申请号：US15596416
申请日：2017-05-16
Applicant: NXP B.V.
Inventor： Gerben Willem de Jong , Mark Pieter van der Heijden , Jozef Reinerus Maria Bergervoet , Tony Vanhoucke , Gian Hoogzaad , Ivan Matkov Zahariev
Abstract: A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.
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