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公开(公告)号：US20230198114A1
公开(公告)日：2023-06-22
申请号：US17558934
申请日：2021-12-22
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer , Waqas Hassan Syed , Ralf Maria Theodoor Pijper , Harish Nandagopal
CPC classification number: H01P1/20372 , H01P1/20381 , H01Q13/206 , H01P5/10
Abstract: A compact planar balun formed on a substrate including a hairpin-shaped conductive microstrip and a single-ended contact. The hairpin-shaped conductive microstrip includes first and second linear segments integrally formed with a U-shaped segment, and a single-ended contact is conductively coupled at a location along the first linear segment. The first and second linear segments each have a first characteristic impedance and are in parallel with each other having a first end forming first and second differential contacts and having a second end. The U-shaped segment has a second characteristic impedance that is less than the first characteristic impedance in order to achieve proper scatter parameter alignment. The U-shaped segment may be generally formed thicker or wider than the linear segments to achieve a reduced characteristic impedance. In the alternative or in addition, co-planer ground metal is formed closer to the U-shaped segment to achieve a reduced characteristic impedance.
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公开(公告)号：US10381447B2
公开(公告)日：2019-08-13
申请号：US15840622
申请日：2017-12-13
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer , Viet Thanh Dinh , Valerie Marthe Girault
IPC: H01L29/40 , H01L29/417 , H01L23/66 , H01L23/528 , H01L29/423 , H01L23/522 , H01L29/78 , H01L27/02
Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
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公开(公告)号：US09342710B2
公开(公告)日：2016-05-17
申请号：US14086276
申请日：2013-11-21
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer
IPC: G06F21/70 , G06K19/073 , H01L23/00 , H01L23/64
CPC classification number: G06F21/70 , G06K19/07309 , G06K19/07372 , H01L23/576 , H01L23/645 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: An apparatus, method and package for electronic tamper detection. In one example, an apparatus, device or package for electronic tamper detection includes: a first inductor positioned at a first distance from a first conductive surface; a first oscillator generating a first frequency in dependence upon the first inductor; and a comparator setting a tamper detected status if the generated first frequency is not within an error tolerance to a pre-stored first frequency. One example of a method for fabricating an electronic tamper detection apparatus, device, or package is also provided.
Abstract translation: 一种用于电子篡改检测的装置，方法和封装。 在一个示例中，用于电子篡改检测的装置，装置或包装包括：位于离第一导电表面第一距离处的第一电感器; 第一振荡器，其根据第一电感器产生第一频率; 如果生成的第一频率不在预先存储的第一频率的误差容限内，则比较器设置篡改检测状态。 还提供了用于制造电子篡改检测装置，装置或包装的方法的一个示例。
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公开(公告)号：US12211840B2
公开(公告)日：2025-01-28
申请号：US17644138
申请日：2021-12-14
Applicant: NXP B.V.
Inventor： Jozef Reinerus Maria Bergervoet , Xin Yang , Mark Pieter van der Heijden , Lukas Frederik Tiemeijer , Alessandro Baiano
IPC: H01L27/08 , H01L21/8234 , H01L23/528 , H01L27/088 , H01L23/532
Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, (470) are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL (470) are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction (602) and a second direction (604) that is orthogonal to the first direction (602); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (606), where the third direction (606) is orthogonal to both the first direction (602) and the second direction (604).
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公开(公告)号：US11742130B2
公开(公告)日：2023-08-29
申请号：US16449673
申请日：2019-06-24
Applicant: NXP B.V.
IPC: H01L27/28 , H01F27/28 , H01L23/522 , H01L23/528 , H01L23/66 , H01L49/02 , H03F3/21 , H03F3/45
CPC classification number: H01F27/2804 , H01L23/5226 , H01L23/5283 , H01L23/66 , H01L28/10 , H03F3/21 , H03F3/45269 , H01F2027/2809
Abstract: An integrated circuit transformer (150) is formed with a primary winding (91) located in at least a first winding layer having a first thickness, a secondary winding (92) located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line (81) located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.
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Patent Agency Ranking
公开(公告)号：US20150143551A1
公开(公告)日：2015-05-21
申请号：US14086276
申请日：2013-11-21
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer
IPC: G06F21/70
CPC classification number: G06F21/70 , G06K19/07309 , G06K19/07372 , H01L23/576 , H01L23/645 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: An apparatus, method and package for electronic tamper detection. In one example, an apparatus, device or package for electronic tamper detection includes: a first inductor positioned at a first distance from a first conductive surface; a first oscillator generating a first frequency in dependence upon the first inductor; and a comparator setting a tamper detected status if the generated first frequency is not within an error tolerance to a pre-stored first frequency. One example of a method for fabricating an electronic tamper detection apparatus, device, or package is also provided.
Abstract translation: 一种用于电子篡改检测的装置，方法和封装。 在一个示例中，用于电子篡改检测的装置，装置或包装包括：位于离第一导电表面第一距离处的第一电感器; 第一振荡器，其根据第一电感器产生第一频率; 如果生成的第一频率不在预先存储的第一频率的误差容限内，则比较器设置篡改检测状态。 还提供了用于制造电子篡改检测装置，装置或包装的方法的一个示例。
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公开(公告)号：US20240395737A1
公开(公告)日：2024-11-28
申请号：US18663503
申请日：2024-05-14
Applicant: NXP B.V.
Inventor： Ralph Matthijs van Schelven , Waqas Hassan Syed , Konstantinos Doris , Lukas Frederik Tiemeijer , Gilles Montoriol , Francis Jean Guy AUVRAY
IPC: H01L23/66 , H01L23/498
Abstract: A package for an integrated circuit, IC, the package comprising an interposer comprising: a first metal layer including a first metal plate; a second metal layer including a second metal plate; and a dielectric layer separating the first metal layer and the second metal layer, wherein the first metal plate and the second metal plate are arranged to form a parallel plate waveguide, PPW, and wherein the first metal plate comprises a slot for receiving one or more differential signals from the IC.
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公开(公告)号：US12003010B2
公开(公告)日：2024-06-04
申请号：US17558934
申请日：2021-12-22
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer , Waqas Hassan Syed , Ralf Maria Theodoor Pijper , Harish Nandagopal
CPC classification number: H01P1/20372 , H01P1/20381 , H01Q13/206 , H01P5/10
Abstract: A compact planar balun formed on a substrate including a hairpin-shaped conductive microstrip and a single-ended contact. The hairpin-shaped conductive microstrip includes first and second linear segments integrally formed with a U-shaped segment, and a single-ended contact is conductively coupled at a location along the first linear segment. The first and second linear segments each have a first characteristic impedance and are in parallel with each other having a first end forming first and second differential contacts and having a second end. The U-shaped segment has a second characteristic impedance that is less than the first characteristic impedance in order to achieve proper scatter parameter alignment. The U-shaped segment may be generally formed thicker or wider than the linear segments to achieve a reduced characteristic impedance. In the alternative or in addition, co-planer ground metal is formed closer to the U-shaped segment to achieve a reduced characteristic impedance.
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公开(公告)号：US20220199617A1
公开(公告)日：2022-06-23
申请号：US17644138
申请日：2021-12-14
Applicant: NXP B.V.
Inventor： Jozef Reinerus Maria Bergervoet , Xin Yang , Mark Pieter van der Heijden , Lukas Frederik Tiemeijer , Alessandro Baiano
IPC: H01L27/088 , H01L23/528 , H01L21/8234
Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, (470) are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL (470) are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction (602) and a second direction (604) that is orthogonal to the first direction (602); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (606), where the third direction (606) is orthogonal to both the first direction (602) and the second direction (604).
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公开(公告)号：US20190181234A1
公开(公告)日：2019-06-13
申请号：US15840622
申请日：2017-12-13
Applicant: NXP B.V.
Inventor： Lukas Frederik Tiemeijer , Viet Thanh Dinh , Valerie Marthe Girault
IPC: H01L29/417 , H01L23/66 , H01L29/40 , H01L29/423 , H01L23/522 , H01L23/528
CPC classification number: H01L29/41758 , H01L23/5226 , H01L23/5283 , H01L23/66 , H01L27/0207 , H01L29/401 , H01L29/42376 , H01L29/785
Abstract: A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.
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