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公开(公告)号：US11923877B2
公开(公告)日：2024-03-05
申请号：US17660392
申请日：2022-04-22
Applicant: NXP B.V.
Inventor： Gian Hoogzaad , Jozef Reinerus Maria Bergervoet , Alexander Simin
CPC classification number: H04B1/006 , H04B1/163 , H04B1/44 , H04B7/0602
Abstract: An antenna switch circuit and an antenna circuit switching method. The circuit includes an antenna port, a termination port (e.g., for disposal of power reflected back from an antenna and received through the antenna port in a transmit mode), and a receive port (e.g., for receiving a signal from the antenna port via the antenna switch circuit in a receive mode). The circuit also includes a first switch coupled between the antenna port and the termination port. The circuit further includes a resonant inductance coupled between the receive port and the node located between the antenna port and the first switch. The circuit also includes a second switch coupled between a reference potential and a node located between the resonant inductance and the receive port.
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公开(公告)号：US11502682B2
公开(公告)日：2022-11-15
申请号：US17350300
申请日：2021-06-17
Applicant: NXP B.V.
Abstract: A radio frequency, RF, switch circuit (201, 301, 401, 501, 601, 701, 751, 801) includes at least one first PiN diode device (252, 352, 452, 552, 652, 752, 852, 945) configured to sink or source a first alternating current; and an impedance inversion circuit (222, 322, 422, 522, 622, 722, 822, 922), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device (254, 354, 454, 554, 654, 754, 854, 945) configured to source or sink a second alternating current; and a bias circuit (330, 430, 530, 630, 830, 930) connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.
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公开(公告)号：US20220014186A1
公开(公告)日：2022-01-13
申请号：US17350300
申请日：2021-06-17
Applicant: NXP B.V.
Abstract: A radio frequency, RF, switch circuit (201, 301, 401, 501, 601, 701, 751, 801) includes at least one first PiN diode device (252, 352, 452, 552, 652, 752, 852, 945) configured to sink or source a first alternating current; and an impedance inversion circuit (222, 322, 422, 522, 622, 722, 822, 922), connected to the at least one first PiN diode device and arranged to provide a transformed impedance between a first side of the impedance inversion circuit and a second side of the impedance inversion circuit. The RF switch further includes a second diode-based device (254, 354, 454, 554, 654, 754, 854, 945) configured to source or sink a second alternating current; and a bias circuit (330, 430, 530, 630, 830, 930) connected to at least one of the at least one first PiN diode device and the second diode-based device, wherein the at least one first PiN diode device cooperates with the second diode-based device as a push-pull current circuit.
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公开(公告)号：US11482974B2
公开(公告)日：2022-10-25
申请号：US17027782
申请日：2020-09-22
Applicant: NXP B.V.
Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
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公开(公告)号：US20190334489A1
公开(公告)日：2019-10-31
申请号：US16354277
申请日：2019-03-15
Applicant: NXP B.V.
Abstract: A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.
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Patent Agency Ranking
公开(公告)号：US20180006612A1
公开(公告)日：2018-01-04
申请号：US15601661
申请日：2017-05-22
Applicant: NXP B.V.
CPC classification number: H03F1/0288 , H01L23/66 , H03F1/565 , H03F3/195 , H03F3/211 , H03F2200/391 , H03F2200/423 , H03F2200/537 , H03F2200/541
Abstract: A Doherty amplifier comprising: a main-power-amplifier having a main-amp-output-terminal; a peaking-power-amplifier having a peaking-amp-output-terminal; a combining node; a main-output-impedance-inverter connected between the main-amp-output-terminal and the combining node; and a transformer connected between the peaking-amp-output-terminal and the combining node.
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公开(公告)号：US20180006021A1
公开(公告)日：2018-01-04
申请号：US15619694
申请日：2017-06-12
Applicant: NXP B.V.
IPC: H01L27/06 , G11C11/412 , H03K3/356 , H03K19/088
CPC classification number: H01L27/0652 , G11C11/412 , H03F1/0288 , H03F1/52 , H03F3/195 , H03F3/213 , H03F3/245 , H03F2200/18 , H03F2200/21 , H03F2200/411 , H03F2200/42 , H03F2200/432 , H03F2200/444 , H03F2200/451 , H03F2200/555 , H03F2200/75 , H03K3/356 , H03K3/356104 , H03K19/088
Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
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公开(公告)号：US20220199617A1
公开(公告)日：2022-06-23
申请号：US17644138
申请日：2021-12-14
Applicant: NXP B.V.
Inventor： Jozef Reinerus Maria Bergervoet , Xin Yang , Mark Pieter van der Heijden , Lukas Frederik Tiemeijer , Alessandro Baiano
IPC: H01L27/088 , H01L23/528 , H01L21/8234
Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, (470) are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL (470) are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction (602) and a second direction (604) that is orthogonal to the first direction (602); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (606), where the third direction (606) is orthogonal to both the first direction (602) and the second direction (604).
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公开(公告)号：US10090295B2
公开(公告)日：2018-10-02
申请号：US15619694
申请日：2017-06-12
Applicant: NXP B.V.
IPC: H03F3/04 , H01L27/06 , H03K19/088 , G11C11/412 , H03K3/356
Abstract: A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
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公开(公告)号：US20210126597A1
公开(公告)日：2021-04-29
申请号：US17027782
申请日：2020-09-22
Applicant: NXP B.V.
Abstract: An RF power amplifier is described including a first amplifier and a second amplifier arranged in parallel between an RF power amplifier input and an RF power amplifier output. A phase adjuster adjusts the phase of a signal on at least one of the first amplifier signal path and the second amplifier signal path. A first impedance inverter has a first impedance inverter input coupled to an output of the second amplifier and a first impedance inverter output coupled to the RF power amplifier output. The RF power amplifier is configured to enable at least one of the first amplifier and the second amplifier dependent on an operation mode and the first impedance inverter is configured to modulate the load impedance of the second amplifier in response to the operation mode changing.
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