中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

30 records (took 0.017 seconds)

    Semiconductor device with an encircled electrode
    2.
    发明授权
    Semiconductor device with an encircled electrode 有权

    公开(公告)号：US10930747B2

    公开(公告)日：2021-02-23

    申请号：US16431056

    申请日：2019-06-04

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Mahmoud Shehab Mohammad Al-Sa'di

    IPC: H01L29/06 ,  H01L29/417 ,  H01L29/868

    Abstract: An embodiment of a semiconductor device includes a first semiconductor region formed within a semiconductor substrate, a second semiconductor region formed within the semiconductor substrate, a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region and proximate the first electrode, wherein the second electrode is encircled by the first electrode. A third electrode may be coupled to the first electrode and the second semiconductor region. A fourth electrode may be coupled to the first semiconductor region and proximate the third electrode, wherein the fourth electrode may be coupled to the second electrode, and wherein the third electrode includes a shared portion of the first electrode.

    Bipolar Transistor
    4.
    发明申请
    Bipolar Transistor 有权
    双极晶体管

    公开(公告)号：US20160079345A1

    公开(公告)日：2016-03-17

    申请号：US14852385

    申请日：2015-09-11

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee ,  Ponky Ivo ,  Dirk Klaassen ,  Mahmoud Shehab Mohammad Al-Sa'di

    IPC: H01L29/06 ,  H01L29/66 ,  H03F3/21 ,  H01L29/417 ,  H01L21/324 ,  H01L29/735 ,  H01L29/08

    CPC classification number: H01L29/063 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378 ,  H03F3/21

    Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

    Abstract translation: 一种包括双极晶体管的半导体器件及其制造方法。 一种功率放大器，包括双极晶体管。 双极晶体管包括具有横向延伸漂移区的集电极。 双极晶体管还包括位于集电极之上的基极。 双极晶体管还包括位于基极上方的发射极。 双极晶体管还包括具有不同于集电极的导电类型的掺杂区域。 掺杂区域在集电极下方横向延伸以在掺杂区域和集电极之间的接触区域处形成结。 掺杂区域具有非均匀的横向掺杂分布。 在最接近双极晶体管的集电极 - 基极结的掺杂区域的一部分中，掺杂区域的掺杂水平最高。

    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT
    5.
    发明申请
    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT 审中-公开
    晶体管放大器电路和集成电路

    公开(公告)号：US20150145005A1

    公开(公告)日：2015-05-28

    申请号：US14542990

    申请日：2014-11-17

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Tony Vanhoucke ,  Evelyne Gridelet ,  Anco Heringa ,  Jan Willem Slotboom ,  Dirk Klaassen

    IPC: H01L29/737 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

    CPC classification number: H01L29/7371 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/735 ,  H01L29/7378 ,  H01L29/7809 ,  H01L29/7835

    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

    Abstract translation: 公开了具有第一导电类型的第一区域用于将电荷载体注入晶体管的第一区域和第二导电类型的横向延伸的第二区域的晶体管，其具有包括用于从晶体管排出所述电荷载流子的接触端子的部分，其中， 第一区域与第二区域通过限定与第一区域的第一pn结的第二导电类型的中间区域和与第二区域的第二pn结分离，其中横向延伸区域将第二pn结部分与第二pn结分离， 并且其中所述晶体管还包括具有所述第二导电类型的掺杂区域的衬底，所述掺杂区域沿着所述横向延伸的第二区域接触并延伸，以及另外的接触端子，其连接到所述掺杂区域，以从所述掺杂区域中排出少数电荷载流子 横向延伸的第二区域。 还公开了包括这种晶体管的放大器电路和IC。

    Transistor amplifier circuit and integrated circuit
    6.
    发明授权
    Transistor amplifier circuit and integrated circuit 有权

    公开(公告)号：US10043894B2

    公开(公告)日：2018-08-07

    申请号：US14542990

    申请日：2014-11-17

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Tony Vanhoucke ,  Evelyne Gridelet ,  Anco Heringa ,  Jan Willem Slotboom ,  Dirk Klaassen

    IPC: H01L29/737 ,  H01L29/06 ,  H01L29/735 ,  H01L29/78 ,  H01L29/165

    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

    PUF METHOD USING AND CIRCUIT HAVING AN ARRAY OF BIPOLAR TRANSISTORS
    7.
    发明申请
    PUF METHOD USING AND CIRCUIT HAVING AN ARRAY OF BIPOLAR TRANSISTORS 审中-公开
    使用和电路的PUF方法具有双极晶体管阵列

    公开(公告)号：US20150028847A1

    公开(公告)日：2015-01-29

    申请号：US14307563

    申请日：2014-06-18

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Viet Nguyen

    IPC: G01R31/28 ,  G01R19/00

    CPC classification number: G01R31/2836 ,  G01R19/0092 ,  G06F21/73 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/805

    Abstract: A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed.

    Abstract translation: 公开了一种通过对挑战的响应来识别组件的方法，该组件包括可并联连接的双极晶体管阵列，以便具有共同的集电极接触，公共发射极接触和公共基极接触，该挑战包括值 代表总集电极电流值，该方法包括：接收挑战; 将总集电极电流提供给公共集电极触点; 检测一组晶体管中的每一个中的不稳定性; 并根据该组确定响应。 还公开了一种配置成操作这种方法的电路。

    METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT
    9.
    发明申请
    METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT 有权
    加工硅晶圆和硅集成电路的方法

    公开(公告)号：US20140167055A1

    公开(公告)日：2014-06-19

    申请号：US14098923

    申请日：2013-12-06

    Applicant: NXP B.V.

    Inventor： Evelyne Gridelet ,  Hans Mertens ,  Michiel Jos van Duuren ,  Tony Vanhoucke ,  Viet Thanh Dinh

    IPC: H01L21/02 ,  H01L27/06

    CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/11546

    Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

    Abstract translation: 公开了用于处理硅晶片的方法和系统。 一种方法包括在硅晶片中提供闪速存储区域，并在硅晶片中提供具有多晶硅外部基极的双极晶体管。 闪存区域和双极晶体管通过沉积闪存区域和双极晶体管两者共同的单个多晶硅层来形成。

Patent Agency Ranking