公开(公告)号：US20160247880A1

公开(公告)日：2016-08-25

申请号：US15013648

申请日：2016-02-02

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Hamza Nijjari

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/76224 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/78

Abstract: A semiconductor device comprising a switch and a method of making the same. The device has a layout that includes one or more rectangular unit cells. Each unit cell includes a gate that divides the unit cell into four corner regions. Each unit cell also includes a source comprising first and second source regions located in respective opposite corner regions of the unit cell. Each unit cell further includes a drain comprising first and second drain regions located in respective opposite corner regions of the unit cell. Each unit cell also includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the gate, source and drain.

Abstract translation: 一种包括开关的半导体器件及其制造方法。 该设备具有包括一个或多个矩形单位单元的布局。 每个单位单元包括将单位单元划分成四个角区域的门。 每个单位单元还包括源，该源包括位于单位单元的相应的相对角区域中的第一和第二源极区域。 每个单电池进一步包括一个漏极，它包括位于晶胞的相应的相对角区域中的第一和第二漏区。 每个单元还包括在栅极，源极和漏极上延伸的多个连接构件，用于提供与栅极，源极和漏极的电连接。

公开(公告)号：US09305697B2

公开(公告)日：2016-04-05

申请号：US14573630

申请日：2014-12-17

Applicant: NXP B.V.

Inventor： Olivier Tesson

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0026 ,  H01F2017/0086 ,  H01F2027/2809

Abstract: An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.

Abstract translation: 一种包括初级线圈和次级线圈的集成变压器，所述初级线圈包括第一子部分和第二子部分，所述第一子部分在不同的平面中延伸到第二子部分延伸的平面，所述平面彼此间隔开， 次级线圈包括第一子部分和第二子部分，第一子部分在不同的平面中延伸到第二子部分延伸的平面，所述平面彼此间隔开，其中初级线圈的第一子部分与第二子部分 并且次级线圈的第二分段与次级线圈的第一分段堆叠在一起。

公开(公告)号：US20130229239A1

公开(公告)日：2013-09-05

申请号：US13781564

申请日：2013-02-28

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Patrice Gamand ,  Sidina Wane

IPC: H01P5/18

CPC classification number: H01P5/186

Abstract: A Lange coupler comprises an unbroken peripheral ground conductor surrounding input, through, coupled and isolated conductor strips coupled to input, through, coupled and isolated ports of the Lange coupler respectively, wherein the peripheral ground conductor and input and through conductor strips are arranged on a first metal layer.

Abstract translation: Lange耦合器包括一个不间断的外围接地导体，其围绕分别耦合到兰格耦合器的输入，通过，耦合和隔离端口的输入，通过，耦合和隔离的导体条，其中外围接地导体和输入和通过导体条布置在 第一金属层。

公开(公告)号：US20200075485A1

公开(公告)日：2020-03-05

申请号：US16523277

申请日：2019-07-26

Applicant: NXP B.V.

Inventor： Olivier Tesson

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01F7/06 ,  H01F27/28

Abstract: An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.

公开(公告)号：US10217735B2

公开(公告)日：2019-02-26

申请号：US15596188

申请日：2017-05-16

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Thomas Francois

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

Abstract: A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor substrate. The field effect transistor includes a plurality of gates. Each gate includes a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate. The loops formed by the gates are arranged concentrically. Each gate has a source region located adjacent an inner edge or outer edge of the loop formed by that gate and a drain region located adjacent the other edge of said inner edge and said outer edge of the loop formed by that gate.

公开(公告)号：US20180211882A1

公开(公告)日：2018-07-26

申请号：US15865867

申请日：2018-01-09

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Thomas Francois

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/417 ,  H01L23/482 ,  H01L29/423

CPC classification number: H01L21/823475 ,  H01L21/76224 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/78

Abstract: A semiconductor device comprising a switch and a method of making the same. The device, has a layout having one or more rectangular unit cells. Each unit cell includes a gate having a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into an inner region located inside the loop-shaped part; and an outer region located outside the loop-shaped part. Each unit cell also includes a substantially loop-shaped active region forming a source and drain of the switch. Each unit cell further includes a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

公开(公告)号：US20150255630A1

公开(公告)日：2015-09-10

申请号：US14635018

申请日：2015-03-02

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Mathieu Perin ,  Laure Rolland du Roscoat

IPC: H01L29/93 ,  H01L29/423

CPC classification number: H01L29/93 ,  H01L23/4824 ,  H01L27/0808 ,  H01L27/0811 ,  H01L29/423 ,  H01L29/66174 ,  H01L29/94 ,  H01L2924/0002 ,  H03B5/124 ,  H03B5/1243 ,  H01L2924/00

Abstract: A MOS varactor structure comprising a semiconductor body having a well region and a plurality of gate electrodes and a plurality of cathode electrodes arranged over the well region, wherein the gate electrodes comprise elongate pads, and the plurality of cathode contacts are connected by a cathode connection pattern, the cathode connection pattern comprising a plurality of arms, each of the plurality of arms arranged to extend over a part of a respective gate electrode pad.

Abstract translation: 一种MOS变容二极管结构，包括具有阱区和多个栅电极的半导体本体和布置在阱区上的多个阴极，其中栅电极包括细长焊盘，并且多个阴极触点通过阴极连接 阴极连接图案包括多个臂，所述多个臂中的每一个布置成在相应的栅电极焊盘的一部分上延伸。

公开(公告)号：US20150170824A1

公开(公告)日：2015-06-18

申请号：US14573630

申请日：2014-12-17

Applicant: NXP B.V.

Inventor： Olivier Tesson

IPC: H01F27/28

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0026 ,  H01F2017/0086 ,  H01F2027/2809

Abstract: An integrated transformer comprising a primary coil and a secondary coil, the primary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, the secondary coil comprising a first subsection and a second subsection, the first subsection extending in a different plane to a plane in which the second subsection extends, the planes spaced from one another, wherein the first subsection of the primary coil is stacked with the second subsection of the secondary coil and the second subsection of the primary coil is stacked with the first subsection of the secondary coil.

Abstract translation: 一种包括初级线圈和次级线圈的集成变压器，所述初级线圈包括第一子部分和第二子部分，所述第一子部分在不同的平面中延伸到第二子部分延伸的平面，所述平面彼此间隔开， 次级线圈包括第一子部分和第二子部分，第一子部分在不同的平面中延伸到第二子部分延伸的平面，所述平面彼此间隔开，其中初级线圈的第一子部分与第二子部分 并且次级线圈的第二分段与次级线圈的第一分段堆叠在一起。

公开(公告)号：US20140036406A1

公开(公告)日：2014-02-06

申请号：US13953539

申请日：2013-07-29

Applicant: NXP B.V.

Inventor： Olivier Tesson ,  Laure Rolland du Roscoat

IPC: H01G7/06

CPC classification number: H01G7/06 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/0808 ,  H01L27/0811 ,  H01L28/86 ,  H01L29/66174 ,  H01L29/93 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A varactor comprises a substrate having sets of gate units each having parallel gate strips. The gate units are located such that the gate strips of neighbouring gate units are oriented transverse to each other. An electrically conducting gate connection layer comprises gate connection units comprising parallel gate connection strips located over the gate strips, and a cathode connection frame around each of the gate connection units. A first electrically conductive anode layer comprises first layer anode strips located parallel to the gate connection strips and connected to alternate gate connection strips, and a first anode connection frame connected to the anode strips. A second electrically conductive anode layer comprises anode strips located parallel to the gate connection strips and connected to opposite alternate gate connection strips, and a second anode connection frame connected to the second layer anode strips.

Abstract translation: 变容二极管包括具有各自具有平行栅极条的栅极单元组的衬底。 栅极单元被定位成使得相邻栅极单元的栅极条彼此横向定向。 导电栅极连接层包括栅极连接单元，栅极连接单元包括位于栅极条上的并联栅极连接条，以及围绕每个栅极连接单元的阴极连接框架。 第一导电阳极层包括平行于栅极连接条并连接到交替栅极连接条的第一层阳极条和连接到阳极条的第一阳极连接框架。 第二导电阳极层包括平行于栅极连接条并连接到相对的交替栅极连接条的阳极条，以及连接到第二层阳极条的第二阳极连接框架。

公开(公告)号：US12170512B2

公开(公告)日：2024-12-17

申请号：US17819794

申请日：2022-08-15

Applicant: NXP B.V.

Inventor： Olivier Tesson

IPC: H03H7/20 ,  H01Q1/52 ,  H01Q3/30 ,  H03H17/08 ,  H01P1/18

Abstract: An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.