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    Clock synchronizer
    11.
    发明授权
    Clock synchronizer 有权

    公开(公告)号：US09973196B2

    公开(公告)日：2018-05-15

    申请号：US15085821

    申请日：2016-03-30

    Applicant: NXP B.V.

    Inventor： Jos Verlinden ,  Remco van de Beek ,  Stefan Mendel

    IPC: H03L7/087 ,  H03L7/197 ,  H03L7/23 ,  H03L7/107 ,  H03L7/18 ,  H04B5/00 ,  H04L7/033 ,  H04W4/00

    CPC classification number: H03L7/087 ,  H03L7/1075 ,  H03L7/1803 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/235 ,  H04B5/0031 ,  H04L7/0331 ,  H04W4/80

    Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

    CONTACTLESS COMMUNICATION DEVICE WITH DIFFERENTIAL RECEIVER INPUT VOLTAGE STABLIZATION
    17.
    发明申请
    CONTACTLESS COMMUNICATION DEVICE WITH DIFFERENTIAL RECEIVER INPUT VOLTAGE STABLIZATION 审中-公开

    公开(公告)号：US20190020374A1

    公开(公告)日：2019-01-17

    申请号：US15646955

    申请日：2017-07-11

    Applicant: NXP B.V.

    Inventor： Jingfeng Ding ,  Gernot Hueber ,  Stefan Mendel

    IPC: H04B5/00 ,  H03L7/08 ,  H03G1/00 ,  G05F3/02

    Abstract: A contactless communication device includes a receiver unit having differential input terminals for connecting to an antenna. The receiver unit is coupled to a transmitting device and receives an RF signal transmitted by the transmitting device. A first comparator is adapted to generate a first comparator output signal indicative of a relationship between a voltage at a positive input terminal of the receiver unit and a first reference voltage. A second comparator is adapted to generate a second comparator output signal indicative of a relationship between a voltage at a negative input terminal of the receiver unit and a second reference voltage. A first voltage regulation circuit is adapted to regulate the voltage at the positive input terminal in response to the first comparator output signal. A second voltage regulation circuit is adapted to regulate the voltage at the negative input terminal in response to the second comparator output signal.

    CLOCK SYNCHRONIZER
    18.
    发明申请
    CLOCK SYNCHRONIZER 有权
    时钟同步器

    公开(公告)号：US20160294398A1

    公开(公告)日：2016-10-06

    申请号：US15085821

    申请日：2016-03-30

    Applicant: NXP B.V.

    Inventor： Jos Verlinden ,  Remco van de Beek ,  Stefan Mendel

    IPC: H03L7/087 ,  H03L7/18 ,  H04W4/00 ,  H04L7/033 ,  H04B5/00 ,  H03L7/107 ,  H03L7/197

    CPC classification number: H03L7/087 ,  H03L7/1075 ,  H03L7/1803 ,  H03L7/197 ,  H03L7/1974 ,  H03L7/235 ,  H04B5/0031 ,  H04L7/0331 ,  H04W4/80

    Abstract: Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

    Abstract translation: 用于时钟同步的装置包括第一锁相环（405）和第二锁相环（400）。 第一锁相环（405）被配置为接收具有参考频率的参考信号（Fcrystal），并且可操作以产生具有作为参考频率倍数的输出频率的输出信号（Fout）。 第一锁相环（405）包括响应于控制信号来控制多个的分频器（428）。 第二锁相环（400）被配置为确定输出信号（Fout）和输入信号（Fantenna）之间的相位误差，并将控制信号提供给第一锁相环（405）。 第二锁相环（400）包括相位调整装置（450），可操作以通过在一段持续时间内改变控制信号来调节输入和输出信号之间的相位差。

    RF device and method with improved active load modulation capability
    19.
    发明授权
    RF device and method with improved active load modulation capability 有权
    RF器件和具有改进的有源负载调制能力的方法

    公开(公告)号：US09401739B2

    公开(公告)日：2016-07-26

    申请号：US14321433

    申请日：2014-07-01

    Applicant: NXP B.V.

    Inventor： Michael Pieber ,  Erich Merlin ,  Stefan Mendel

    IPC: H04B1/44 ,  H04B5/00 ,  H04B5/02

    CPC classification number: H04B1/44 ,  H04B5/0075 ,  H04B5/02

    Abstract: There is described an RF bidirectional communication device utilizing active load modulation, the device comprising (a) a resonance circuit including an antenna (326), and (b) a control unit (322) for controlling communication of the device, including switching between a transmission mode and a receiving mode, wherein the control unit is adapted to (c) modify a configuration of the resonance circuit such that the resonance circuit has a first resonance frequency (f0) when the device is in the transmission mode and a second resonance frequency (f0+Δf) when the device is in the receiving mode, and (d) modify the configuration of the resonance circuit such that a Q-factor of the resonance circuit is periodically decreased while the device is in the transmission mode. There is also described a corresponding method and a system comprising a RF device and a reader/writer device. Furthermore, there is described a computer program and a computer program product.

    Abstract translation: 描述了利用有源负载调制的RF双向通信装置，该装置包括（a）包括天线的谐振电路（326）和（b）用于控制装置的通信的控制单元（322），包括在 传输模式和接收模式，其中所述控制单元适于（c）修改所述谐振电路的配置，使得当所述设备处于所述传输模式时所述谐振电路具有第一谐振频率（f0），并且所述谐振电路具有第二谐振频率 （f0 +Δf），以及（d）修改谐振电路的结构，使得谐振电路的Q因子在器件处于传输模式时周期性地减小。 还描述了包括RF设备和读取器/写入器设备的相应方法和系统。 此外，描述了计算机程序和计算机程序产品。

    Communications device and method for operating a communications device
    20.
    发明授权
    Communications device and method for operating a communications device 有权

    公开(公告)号：US11206170B2

    公开(公告)日：2021-12-21

    申请号：US16704262

    申请日：2019-12-05

    Applicant: NXP B.V.

    Inventor： Ulrich Andreas Muehlmann ,  Stefan Mendel ,  Steve Charpentier

    IPC: H04L27/36 ,  H04L27/38 ,  H03D7/14

    Abstract: Embodiments of communications devices and methods for operating a communications device are described. In an embodiment, a communications device includes a complex multiplier configured to multiply a first input complex signal with a second input complex signal to generate an output complex signal, an amplifier configured to amplify an imaginary part of the output complex signal to generate an amplification result, a delay element configured to delay a rotation angle signal that is related to the second input complex signal, and a subtractor configured to subtract the amplification result from the delayed rotation angle signal to generate the rotation angle signal. Other embodiments are also described.

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