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    Systems and Methods for Parameter Modification During Data Processing Retry
    12.
    发明申请
    Systems and Methods for Parameter Modification During Data Processing Retry 有权
    数据处理重试期间参数修改的系统和方法

    公开(公告)号：US20130208376A1

    公开(公告)日：2013-08-15

    申请号：US13372600

    申请日：2012-02-14

    申请人： Shaohua Yang ,  Jin Lu ,  Haitao Xia

    发明人： Shaohua Yang ,  Jin Lu ,  Haitao Xia

    IPC分类号： G11B5/09

    CPC分类号： G11B5/09 ,  G11B20/10009

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了包括缓冲电路，均衡器电路，数据处理电路和重试确定电路的数据处理系统。 缓冲器可操作以将数字样本存储为缓冲输出，并且均衡器电路可操作以使用第一均衡目标来均衡缓冲输出，以产生第一均衡输出，并且使用第二均衡目标产生第二均衡输出。 重试确定电路可操作以至少部分地基于错误的发生来选择第二均衡目标。

    Systems and Methods for Adaptive Gain Control
    13.
    发明申请
    Systems and Methods for Adaptive Gain Control 有权
    自适应增益控制的系统和方法

    公开(公告)号：US20130176640A1

    公开(公告)日：2013-07-11

    申请号：US13346556

    申请日：2012-01-09

    申请人： Haitao Xia ,  Yu Liao

    发明人： Haitao Xia ,  Yu Liao

    IPC分类号： G11B5/09 ,  G11B5/02 ,  H03M1/12

    CPC分类号： H03M1/185 ,  G11B20/10009

    摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an analog to digital converter circuit, a data detector circuit, a filter circuit, an error generation circuit, and a target parameter adaptation circuit. The analog to digital converter circuit converts an analog input into corresponding digital samples. The data detector circuit applies a data detection algorithm to a data set derived from the digital samples to yield a detected output. The filter circuit convolves the detected output with a target parameter to yield a target output. The error generation circuit calculates an error value based on the digital samples and the target output. The target parameter adaptation circuit updates the target parameter based at least in part on the error value.

    摘要翻译： 本发明的各种实施例提供了用于数据处理的系统和方法。 例如，讨论了一种数据处理系统，其包括：模数转换器电路，数据检测器电路，滤波器电路，误差产生电路和目标参数自适应电路。 模数转换器电路将模拟输入转换为相应的数字采样。 数据检测器电路将数据检测算法应用于从数字样本导出的数据集，以产生检测到的输出。 滤波器电路将检测到的输出与目标参数进行卷积以产生目标输出。 误差产生电路根据数字采样和目标输出来计算误差值。 目标参数自适应电路至少部分地基于误差值更新目标参数。

    Systems and Methods for Mitigating Stubborn Errors in a Data Processing System
    15.
    发明申请
    Systems and Methods for Mitigating Stubborn Errors in a Data Processing System 有权
    缓解数据处理系统中固有错误的系统和方法

    公开(公告)号：US20130024740A1

    公开(公告)日：2013-01-24

    申请号：US13186234

    申请日：2011-07-19

    申请人： Haitao Xia ,  Wu Chang ,  Shaohua Yang

    发明人： Haitao Xia ,  Wu Chang ,  Shaohua Yang

    IPC分类号： H03M13/03 ,  G06F11/10

    CPC分类号： H03M13/1102 ,  H03M13/1515 ,  H03M13/2957 ,  H03M13/3746 ,  H03M13/41 ,  H03M13/42 ,  H03M13/451 ,  H03M13/458 ,  H03M13/6331

    摘要： Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.

    摘要翻译： 本发明的各种实施例提供数据处理电路，其包括：数据检测器电路，数据解码器电路和修改电路。 数据检测器电路可操作以将数据检测算法应用于数据输入以产生检测到的输出。 数据解码器电路可操作以将数据解码算法应用于解码输入以产生解码输出。 在至少检测到的输出和检测到的输出的修改版本之间选择解码输入。 修改电路可操作以接收所检测的输出并提供所检测输出的修改版本。

    Systems and Methods for Early Stage Noise Compensation in a Detection Channel
    16.
    发明申请
    Systems and Methods for Early Stage Noise Compensation in a Detection Channel 审中-公开
    检测通道中早期噪声补偿的系统和方法

    公开(公告)号：US20130024163A1

    公开(公告)日：2013-01-24

    申请号：US13186251

    申请日：2011-07-19

    申请人： Haitao Xia ,  Shaohua Yang ,  Ming Jin

    发明人： Haitao Xia ,  Shaohua Yang ,  Ming Jin

    IPC分类号： G06F15/00

    CPC分类号： G11B20/10203 ,  G11B20/10296 ,  G11B2220/2516

    摘要： Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output.

    摘要翻译： 本发明的各种实施例提供数据处理电路，其包括：数据检测器电路，数据解码器电路和修改电路。 数据检测器电路可操作以将数据检测算法应用于数据输入以产生检测到的输出。 数据解码器电路可操作以将数据解码算法应用于解码输入以产生解码输出。 在至少检测到的输出和检测到的输出的修改版本之间选择解码输入。 修改电路可操作以接收所检测的输出并提供所检测输出的修改版本。

    Storage media defect detection
    17.
    发明授权
    Storage media defect detection 有权
    存储介质缺陷检测

    公开(公告)号：US08274871B2

    公开(公告)日：2012-09-25

    申请号：US13291017

    申请日：2011-11-07

    申请人： Haitao Xia ,  Yenyu Hsieh ,  Bac Pham

    发明人： Haitao Xia ,  Yenyu Hsieh ,  Bac Pham

    IPC分类号： G11B20/18

    CPC分类号： G11B20/18 ,  G11B20/10037 ,  G11B20/10222 ,  G11B27/36 ,  G11B2020/1826 ,  G11B2220/2516

    摘要： Detecting a defect on a storage device is disclosed. Detecting includes receiving a signal read from a storage device, sampling the signal to obtain a set of signal samples, wherein the sampling starts at an arbitrary time, computing a defect value for a defect type using the set of signal samples, comparing the defect value with a threshold associated with the defect type, determining whether there is a defect of the defect type based at least in part on the comparison, and in the event that a defect is detected, outputting an indication associated with the defect.

    摘要翻译： 公开了检测存储设备上的缺陷。 检测包括接收从存储设备读取的信号，对信号进行采样以获得一组信号样本，其中采样在任意时间开始，使用该组信号样本计算缺陷类型的缺陷值，比较缺陷值 具有与缺陷类型相关联的阈值，至少部分地基于比较来确定是否存在缺陷类型的缺陷，并且在检测到缺陷的情况下，输出与缺陷相关联的指示。

    PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS
    18.
    发明申请
    PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS 有权
    前瞻性收购，没有第二个订单时机

    公开(公告)号：US20110075779A1

    公开(公告)日：2011-03-31

    申请号：US12960043

    申请日：2010-12-03

    申请人： Haitao Xia ,  Shih-Ming Shih ,  Ryan Yu ,  Marcus Marrow ,  Kai Keung Chan

    发明人： Haitao Xia ,  Shih-Ming Shih ,  Ryan Yu ,  Marcus Marrow ,  Kai Keung Chan

    IPC分类号： H04L7/00

    CPC分类号： H04L7/08

    摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.

    摘要翻译： 通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。 使用时钟对第一多个采样和第二多个采样进行采样。 至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。 至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。 时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。