公开(公告)号：US20060223152A1

公开(公告)日：2006-10-05

申请号：US10553394

申请日：2004-04-16

申请人： Kazumi Okuro ,  Susumu Amano ,  Noriyuki Kizaki ,  Teruaki Takesue ,  Masaru Mitsuda ,  Noriyuki Ito ,  Yoshihiko Yasohara

发明人： Kazumi Okuro ,  Susumu Amano ,  Noriyuki Kizaki ,  Teruaki Takesue ,  Masaru Mitsuda ,  Noriyuki Ito ,  Yoshihiko Yasohara

IPC分类号： C12P13/00 ,  C07F3/02

CPC分类号： C07C233/18 ,  C07B2200/07 ,  C07C51/06 ,  C07C67/20 ,  C07C233/05 ,  C07C271/64 ,  C12P7/40 ,  C12P41/005 ,  C07C57/03 ,  C07C69/533

摘要： The present invention provides a process for producing an optically active 2-allylcarboxylic acid derivative, which is useful as a pharmaceutical intermediate, from readily available and inexpensive starting materials by the process which can be practiced on a commercial scale in a simple and easy manner, and certain 2-allylcarboxamide derivatives, which are novel and important intermediates in that process. An N-allylcarboxamide derivative undergoes rearrangement reaction diastereoselectively in the presence of a base to give a 2-allylcarboxamide derivative, the resulting derivative is subjected to a carbamation reaction and solvolysis to give an optically active 2-allylcarboxylic acid ester, and then the ester obtained is stereoselectively hydrolyzed using an enzyme to produce 2-allylcarboxylic acid having a high optical purity. In addition, the present invention provides a 2-allylcarboxamide derivative compound which is a novel intermediate in the process of the present invention.

摘要翻译： 本发明提供了一种用于制备可用作药物中间体的光学活性2-烯丙基羧酸衍生物的方法，其由易于获得且廉价的原料通过可以简单和容易的方式在商业规模上实施的方法制备， 和某些2-烯丙基羧酰胺衍生物，它们是该方法中新颖且重要的中间体。 N-烯丙基甲酰胺衍生物在碱存在下非对映选择性地进行重排反应，得到2-烯丙基甲酰胺衍生物，所得衍生物进行氨基甲酰化反应和溶剂解，得到光学活性2-烯丙基羧酸酯，然后得到所述酯 使用酶进行立体选择性水解以产生具有高光学纯度的2-烯丙基羧酸。 此外，本发明提供了在本发明的方法中是新型中间体的2-烯丙基甲酰胺衍生物化合物。

公开(公告)号：US07065859B2

公开(公告)日：2006-06-27

申请号：US10725407

申请日：2003-12-03

申请人： Koichi Terunuma ,  Tetsuya Mino ,  Katsuya Kanakubo ,  Noriyuki Ito

发明人： Koichi Terunuma ,  Tetsuya Mino ,  Katsuya Kanakubo ,  Noriyuki Ito

IPC分类号： G11B5/193 ,  B44C1/22 ,  C25D5/02

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G11B5/3116 ,  G11B5/313 ,  G11B5/3153 ,  G11B5/3163 ,  G11B5/3909 ,  G11B5/3967 ,  G11B2005/3996 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49052

摘要： A first magnetic film is formed in a primary pattern which is larger than its definitive pattern and of which edges are located within frames to be used in a frame-plating method for the second magnetic film after forming the first pole portion and the gap film. Then, the second magnetic film is formed by the frame-plating method, and the first magnetic film is etched into the definitive pattern through the second magnetic film as a mask.

摘要翻译： 第一磁性膜以形成第一极部和间隙膜的第二磁性膜的第一磁性膜形成为大于其定形图案的主图案，并且其边缘位于用于第二磁性膜的框架镀覆方法的框架内。 然后，通过框架镀法形成第二磁性膜，并且通过第二磁性膜作为掩模将第一磁性膜蚀刻到确定的图案中。

公开(公告)号：US06751070B2

公开(公告)日：2004-06-15

申请号：US10153689

申请日：2002-05-24

申请人： Noriyuki Ito ,  Kosuke Tanaka ,  Koichi Terunuma

发明人： Noriyuki Ito ,  Kosuke Tanaka ,  Koichi Terunuma

IPC分类号： G11B539

CPC分类号： B82Y10/00 ,  G11B5/3163 ,  G11B5/3903 ,  G11B5/3932 ,  G11B5/3967 ,  Y10T29/49052

摘要： A first and a second longitudinal bias-applying films are formed via a first mask at both sides of a magnetoresistive effective element film so that the difference in surface level between the magnetoresistive effective element film and the first and the second longitudinal bias-applying films is set within ±20 nm. Then, a first and a second electrode films are formed so as to cover edge portions of the magnetoresistive effective element film and the first and the second longitudinal bias-applying films.

摘要翻译： 通过第一掩模在磁阻有效元件膜的两侧形成第一和第二纵向偏置施加膜，使得磁阻有效元件膜与第一和第二纵向偏置施加膜之间的表面水平差异为 设置在±20 nm以内。 然后，形成第一和第二电极膜，以覆盖磁阻有效元件膜和第一和第二纵向偏置施加膜的边缘部分。

公开(公告)号：US06664817B2

公开(公告)日：2003-12-16

申请号：US10323925

申请日：2002-12-20

申请人： Yasuhiro Nakata ,  Noriyuki Ito

发明人： Yasuhiro Nakata ,  Noriyuki Ito

IPC分类号： H03K532

CPC分类号： H03K5/1536 ,  G01R19/175 ,  H02M1/083

摘要： In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.

摘要翻译： 在包括由商用交流电源通过两条电源线供电的全波整流和平滑电路的电源装置中，用于分离和降低全波整流和平滑电路的输出的开关调节器，以输出所需的 直流电压和两个电容器之间的全波整流平滑电路进行终端噪声抑制的目的，零交叉检测电路包括一个晶体管，其发射极连接到全波整流的低压输出端 以及用于从所述收集器输出过零检测信号的平滑电路; 第一电阻器连接在晶体管的基极和发射极之间; 第二电阻器连接在电源线之一和晶体管的基极之间; 并且第三电阻器连接在另一个电源线和晶体管的发射极之间。

公开(公告)号：US5889682A

公开(公告)日：1999-03-30

申请号：US951480

申请日：1997-10-16

申请人： Masayuki Omura ,  Noriyuki Ito

发明人： Masayuki Omura ,  Noriyuki Ito

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H05K1/02 ,  H05K3/00 ,  G06F17/00

CPC分类号： G06F17/5077 ,  H05K1/0237 ,  H05K3/0005

摘要： A clock routing design method enables a routing design for each hierarchy while paying an attention to each layout hierarchy to which a branch of a clock signal system extends and considering a whole chip. In the clock routing design method, a clock signal line is routed between a plurality of receiver terminals over a plurality of layout hierarchies while considering an equal-delay branch point yielding equal delays of a clock signal at the receiver terminals, the clock signal line is then routed between the equal-delay branch point positioning between the plural receiver terminals and the driver terminal. The clock routing design method is applicable to a layout design of wire patterns, cell, etc. on LSIs, printed circuit boards and the like.

摘要翻译： 时钟路由设计方法使得能够对每个层级进行路由设计，同时注意时钟信号系统的分支延伸并考虑整个芯片的每个布局层次。 在时钟路由设计方法中，时钟信号线在多个布局层次之间在多个接收机终端之间路由，同时考虑在接收机端产生时钟信号的相等延迟的等延迟分支点，时钟信号线是 然后在多个接收机终端和驱动器终端之间的等延迟分支点之间路由。 时钟路由设计方法适用于LSI，印刷电路板等上的线图，单元等的布局设计。

公开(公告)号：US09244401B2

公开(公告)日：2016-01-26

申请号：US12607007

申请日：2009-10-27

申请人： Goichi Kitadai ,  Daisuke Miyagawa ,  Noriyuki Ito ,  Takahiro Uchiyama

发明人： Goichi Kitadai ,  Daisuke Miyagawa ,  Noriyuki Ito ,  Takahiro Uchiyama

IPC分类号： G03G15/00 ,  G03G15/20

CPC分类号： G03G15/2042

摘要： In an image forming apparatus, the overall length of a heat generating resistor is set longer than the width of a recording paper, which is the greatest of widths of standard size recording papers that can be used on the image forming apparatus. An electrical resistance of an edge area of the heat generating resistor per unit length is set smaller than that of a center area of the heat generating resistor. The position of a boundary between the center area and the edge area is set so that the position of the side edge of the recording paper whose width is the greatest exists within the edge area and so that if the recording paper having the second greatest width is fed by a one edge-aligned paper feeding method, the position of the side edge of a recording paper whose width is the greatest of the widths of the standard size recording papers that can be used on the image forming apparatus except the width of the recording paper that is the greatest thereof is set at a position within the center area.

摘要翻译： 在图像形成装置中，发热电阻器的总长度被设定为比可以用于图像形成装置的标准尺寸的记录纸的宽度最大的记录纸的宽度长。 每单位长度的发热电阻器的边缘区域的电阻被设定为小于发热电阻器的中心区域的电阻。 中心区域和边缘区域之间的边界的位置被设置为使得宽度最大的记录纸的侧边缘的位置存在于边缘区域内，并且如果具有第二大宽度的记录纸是 通过一个边缘对齐的送纸方式进给，其宽度是除了记录宽度之外可以用于图像形成装置的标准尺寸记录纸的宽度的最大的记录纸的侧边缘的位置 其最大的纸被设置在中心区域内的位置。

公开(公告)号：US20130196389A1

公开(公告)日：2013-08-01

申请号：US13876412

申请日：2011-09-28

申请人： Noriyuki Ito ,  Akiko Nishi ,  Shigeru Kawano ,  Yoshihiko Yasohara

发明人： Noriyuki Ito ,  Akiko Nishi ,  Shigeru Kawano ,  Yoshihiko Yasohara

IPC分类号： C12N9/10

CPC分类号： C12N9/1096 ,  C12P17/10 ,  C12P41/006 ,  C12Y206/01 ,  Y02P20/52

摘要： A method for inexpensively and efficiently producing an optically active amino compound useful as an intermediate for pharmaceutical preparations, agricultural chemicals, or the like, from a ketone compound is provided. Specifically, a polypeptide exhibiting higher activity for glutamic acid as an amino donor than that for L-alanine, and, having novel transaminase activity for generating (S)-1-benzyl-3-pyrrolidinone with high optical purity of 93% or more, a gene encoding the same, and a transformant expressing the gene at a high level are also provided herein.

摘要翻译： 提供了一种从酮化合物廉价有效地制备用作药物制剂，农药等的中间体的旋光性氨基化合物的方法。 具体而言，对于产生具有93％以上光学纯度的（S）-1-苄基-3-吡咯烷酮的新型转氨酶活性，作为氨基供体的谷氨酸比L-丙氨酸具有较高活性的多肽， 本发明还提供了编码该基因的基因，以及高水平表达该基因的转化体。

公开(公告)号：US08407021B2

公开(公告)日：2013-03-26

申请号：US12893362

申请日：2010-09-29

申请人： Noriyuki Ito

发明人： Noriyuki Ito

IPC分类号： G06F19/00

CPC分类号： G06F17/5031

摘要： A delay analysis device includes an acquisition section that acquires circuit information relating to a path through which signal propagation can be delayed, a determination section that sets up an assumed fault for each of pins disposed in the path, and determines whether a signal change output from a beginning latch can be propagated to an ending latch for each of pins for which the assumed faults are set up, and an analysis section that calculates a delay distribution by accumulating delay distributions expressed by probability density functions of delays that occur in individual delay elements included in the path determined that a signal change output from the beginning latch can be propagated to the ending latch, and by not accumulating the delay distributions at a pin through which it has been determined that the signal change cannot be propagated to the ending latch based on the acquired circuit information.

摘要翻译： 延迟分析装置包括：获取部，其获取与可以延迟信号传播的路径有关的电路信息;确定部，其针对设置在路径中的每个引脚设置假设故障，并且确定是否从 可以将开始锁存器传播到针对假设故障建立的每个引脚的结束锁存器，以及分析部件，其通过累积由包括在各个延迟元件中出现的延迟的概率密度函数所表示的延迟分布来计算延迟分布 在该路径中，确定从开始锁存器输出的信号变化可以传播到结束锁存器，并且通过不在其引脚上累积延迟分布，通过该引脚已经确定信号改变不能传播到结束锁存器，基于 获取的电路信息。

公开(公告)号：US07855572B2

公开(公告)日：2010-12-21

申请号：US12662338

申请日：2010-04-12

申请人： Noriyuki Ito

发明人： Noriyuki Ito

IPC分类号： G01R31/26

CPC分类号： G01R31/3016 ,  G01R31/31718

摘要： A variation in manufacturing total costs is obtained by using an excessive loss amount caused by unnecessarily discarding elemental semiconductor integrated circuits occurring as a result of a negative result being obtained in an elemental test but a positive result obtained from a device test, and a short loss amount caused by packaging elemental semiconductor integrated circuits for semiconductor integrated circuit devices that are discarded as a result of a positive result being obtained from the elemental test but a negative result being obtained from the device test. A new operating frequency is determined by using the variation in manufacturing total costs with respect to an operating frequency.

摘要翻译： 制造总成本的变化通过使用由于在元素测试中获得的负面结果而产生的元素半导体集成电路不必要地丢弃而导致的过度损失量，但是从器件测试获得的肯定结果和短的损耗 由于从元件测试获得正结果而丢弃的半导体集成电路器件的元件半导体集成电路的封装所引起的数量，而是从器件测试获得的否定结果。 通过使用相对于工作频率的制造总成本的变化来确定新的工作频率。

公开(公告)号：US07757188B2

公开(公告)日：2010-07-13

申请号：US11785430

申请日：2007-04-17

申请人： Noriyuki Ito

发明人： Noriyuki Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In the present invention, a block level net list is separated from a chip level net list so that the chip level net list can be created in a form in which a block is transparent to a designer. The present invention determines a destination block for circuit elements that are described in a chip level net list and for which the destination block is not determined, and creates a final net list by reflecting the chip level net list to the block level net list based on the information on the destination block. As a net list can be created in a form in which a block is transparent to a designer for a circuit system that is required to be optimized for the entire chip, the circuit system can be efficiently optimized.

摘要翻译： 在本发明中，将块级网表从芯片级网表中分离出来，使得可以以块对设计者透明的形式来创建芯片级网表。 本发明确定在芯片级网表中描述的电路元件的目的地块，并且未确定目的地块，并且通过基于块级网络列表反映芯片级网络列表来创建最终网列表 目的地块上的信息。 由于网络列表可以以对于需要针对整个芯片进行优化的电路系统的设计者是透明的形式来创建，所以可以有效地优化电路系统。