公开(公告)号：US20050012522A1

公开(公告)日：2005-01-20

申请号：US10708284

申请日：2004-02-23

Applicant: Pao-Cheng Chiu ,  Mu-Jung Chen

Inventor： Pao-Cheng Chiu ,  Mu-Jung Chen

IPC: H03K19/0185 ,  H03K19/094

CPC classification number: H03K19/018521

Abstract: A high-to-low level shifter, coupled to a first external signal, for transforming the first external signal into an internal signal, wherein the first external signal substantially switches between a high-voltage-domain high potential and a high-voltage-domain low potential, the internal signal substantially switches between a low-voltage-domain high potential and a low-voltage-domain low potential. The high-to-low level shifter includes: an inverter, for generating a second external signal according to the first external signal, wherein the second external signal is inverse to the first external signal; and a level shifter, for generating the internal signal according to the first external signal and the second external signal.

Abstract translation: 耦合到第一外部信号的高到低电平移位器，用于将第一外部信号变换为内部信号，其中第一外部信号基本上在高电压域高电位和高电压域之间切换 低电位，内部信号基本上在低电压域高电位和低电压域低电位之间切换。 高电平移位器包括：逆变器，用于根据第一外部信号产生第二外部信号，其中第二外部信号与第一外部信号相反; 以及电平移位器，用于根据第一外部信号和第二外部信号产生内部信号。

公开(公告)号：US07973576B2

公开(公告)日：2011-07-05

申请号：US12124201

申请日：2008-05-21

Applicant: Pao-Cheng Chiu

Inventor： Pao-Cheng Chiu

IPC: H03L7/06

CPC classification number: H03K3/0322 ,  H03L7/087 ,  H03L7/0995 ,  H03L2207/06

Abstract: A voltage controlled oscillator comprising first and second differential delay cells. The first differential delay cell has a first control voltage input terminal. The second differential delay cell is coupled to the first differential delay cell in a loop and has a second control voltage input terminal. The second voltage input terminal is disconnected from the first voltage control input terminal. The first voltage control input terminal receives a first voltage signal, and the second voltage control input terminal receives a second voltage signal different from the first voltage signal.

Abstract translation: 一种压控振荡器，包括第一和第二差分延迟单元。 第一差分延迟单元具有第一控制电压输入端。 第二差分延迟单元在环路中耦合到第一差分延迟单元并具有第二控制电压输入端。 第二电压输入端与第一电压控制输入端断开。 第一电压控制输入端子接收第一电压信号，第二电压控制输入端子接收与第一电压信号不同的第二电压信号。

公开(公告)号：US20080218212A1

公开(公告)日：2008-09-11

申请号：US12120520

申请日：2008-05-14

Applicant: Pao-Cheng Chiu

Inventor： Pao-Cheng Chiu

IPC: H03K19/094

CPC classification number: H03K19/018514 ,  H03K19/094 ,  H03M9/00

Abstract: A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled to a second fixed voltage. The low voltage transistor has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage data signal, and a third terminal. The high voltage transistor has a first terminal coupled to the third terminal of the low voltage transistor, a second terminal coupled to a bias source, and a third terminal coupled to the output.

公开(公告)号：US07212044B2

公开(公告)日：2007-05-01

申请号：US10978628

申请日：2004-11-01

Applicant: Chih-Wen Huang ,  Pao-Cheng Chiu

Inventor： Chih-Wen Huang ,  Pao-Cheng Chiu

IPC: H03B1/00

CPC classification number: H04L25/0278 ,  H04L25/028

Abstract: A signal transmitting apparatus being used in a network device includes a voltage-controlled current source for outputting a current signal according to an input digital signal; a line driver for outputting a voltage signal according to the current signal; at least one impedance-matching unit, which is coupled to the line driver, for impedance-matching at the output of the line driver; and a first correction unit, which is coupled to the voltage-controlled current source, for outputting a first correction signal to adjust the current signal outputted from the voltage-controlled current source.

Abstract translation: 在网络装置中使用的信号发送装置包括用于根据输入数字信号输出电流信号的压控电流源; 线驱动器，用于根据当前信号输出电压信号; 耦合到线路驱动器的至少一个阻抗匹配单元，用于在线路驱动器的输出处进行阻抗匹配; 以及第一校正单元，其耦合到压控电流源，用于输出第一校正信号以调整从压控电流源输出的电流信号。

公开(公告)号：US06803796B2

公开(公告)日：2004-10-12

申请号：US10156341

申请日：2002-05-28

Applicant: Chen-Chih Huang ,  Pao-Cheng Chiu

Inventor： Chen-Chih Huang ,  Pao-Cheng Chiu

IPC: H03K1700

CPC classification number: H03L7/0814 ,  H04L7/0083 ,  H04L7/0337

Abstract: The present invention is to provide a multiple phases switching circuit which is operable with a multiple phase signal generator and a succeeding circuit. The multiple-phase signal generator generates N multiple-phase clock signals. Phases of the multiple-phase clock signals are different. The multiple phases switching circuit comprises an alternative signal generator and a multiplexer. The alternative signal generator outputs an alternative signal according to an up/down switching signal. The multiplexer is coupled to the alternative signal generator for receiving the multiple-phase clock signals and proceeding a glitch/spike preventing process according to the alternative signal so as to output a target clock signal to the succeeding circuit.

Abstract translation: 本发明提供一种多相切换电路，其可与多相信号发生器和后续电路一起使用。 多相信号发生器产生N个多相时钟信号。 多相时钟信号的相位是不同的。 多相切换电路包括备用信号发生器和多路复用器。 替代信号发生器根据上/下切换信号输出替代信号。 复用器耦合到替代信号发生器，用于接收多相时钟信号，并根据替代信号进行毛刺/尖峰防止处理，以将目标时钟信号输出到后续电路。

公开(公告)号：US06727741B2

公开(公告)日：2004-04-27

申请号：US10079866

申请日：2002-02-21

Applicant: Chen-Chih Huang ,  Pao-Cheng Chiu

Inventor： Chen-Chih Huang ,  Pao-Cheng Chiu

IPC: H03K513

CPC classification number: H03K5/088 ,  H03K5/13 ,  H03K2005/00286

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract translation: 本发明涉及一种应用相位插值电路的相位插值电路和相位插值信号产生电路。 相位插补电路可以有效地避免短路电流。 此外，可以在时钟脉冲的上升沿和下降沿之间插入相间信号。 相位插值信号发生装置可以产生不仅具有线性分布相位而且维持多相时钟信号的良好的50％占空比的多相时钟信号。

公开(公告)号：US07948411B2

公开(公告)日：2011-05-24

申请号：US12775543

申请日：2010-05-07

Applicant: Zwei-Mei Lee ,  Kang-Wei Hsueh ,  Ya-Lun Yang ,  Hung-Sung Li ,  Pao-Cheng Chiu

Inventor： Zwei-Mei Lee ,  Kang-Wei Hsueh ,  Ya-Lun Yang ,  Hung-Sung Li ,  Pao-Cheng Chiu

IPC: H03M1/00

CPC classification number: H03M1/1038 ,  H03M1/0682 ,  H03M1/1245

Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.

Abstract translation: 提供了一个跟踪和保持放大器。 轨道和保持放大器包括接收模拟信号的输入节点，耦合在第一节点和输出节点之间的缓冲器，耦合在输入节点和第一节点之间的第一开关，多个开关电路和电压产生单元。 每个开关电路包括耦合在第一节点和第二节点之间的电容器。 电压产生单元选择性地向切换电路的电容器提供公共信号或参考信号，其中参考信号独立于模拟信号。

公开(公告)号：US07924062B2

公开(公告)日：2011-04-12

申请号：US12503105

申请日：2009-07-15

Applicant: Pao-Cheng Chiu

Inventor： Pao-Cheng Chiu

IPC: G11C27/02

CPC classification number: G11C27/026 ,  H03K5/249

Abstract: A sampling circuit includes an amplifier, a sampling capacitor, a feedback capacitor, and a voltage source. The sampling capacitor and the feedback capacitor are coupled to the same input terminal of the amplifier, such that the offset of the amplifier and low-frequency noise can be cancelled. The voltage source can shift the voltage level of an output signal of the sampling circuit by the difference between the input and output common mode voltages of the amplifier, so that an amplifier having different input common mode voltage and output common mode voltage can be adopted, and the capacitance of the sampling capacitor and that of the feedback capacitor can be different, resulting in a non-unit gain.

Abstract translation: 采样电路包括放大器，采样电容器，反馈电容器和电压源。 采样电容器和反馈电容器耦合到放大器的相同输入端，使得放大器的偏移和低频噪声可以被消除。 电压源可以通过放大器的输入和输出共模电压之间的差异来移位采样电路的输出信号的电压电平，从而可以采用具有不同输入共模电压和输出共模电压的放大器， 并且采样电容器和反馈电容器的电容可以不同，导致非单位增益。

公开(公告)号：US07738408B2

公开(公告)日：2010-06-15

申请号：US10907046

申请日：2005-03-17

Applicant: Pao-Cheng Chiu ,  Chen-Chih Huang

Inventor： Pao-Cheng Chiu ,  Chen-Chih Huang

IPC: H04L5/14

CPC classification number: H04L5/1461

Abstract: A transceiver in a full duplex communication system includes a hybrid circuit for transmitting a transmission signal or receiving a receive signal via the channel, the hybrid circuit includes an echo cancellation device for removing transmission signal components from the receive signal; wherein the hybrid circuit outputs a processed receive signal; and a gain amplifier being an OP-RC AGC is directly connected to the hybrid circuit for amplifying the processed receive signal, wherein a first node of the gain amplifier coupled to the echo cancellation device is a virtual ground.

Abstract translation: 全双工通信系统中的收发器包括用于经由信道发送发送信号或接收接收信号的混合电路，该混合电路包括用于从接收信号中去除发送信号分量的回波消除装置; 其中所述混合电路输出经处理的接收信号; 并且作为OP-RC AGC的增益放大器直接连接到用于放大经处理的接收信号的混合电路，其中耦合到回声消除装置的增益放大器的第一节点是虚拟接地。

公开(公告)号：US07466179B2

公开(公告)日：2008-12-16

申请号：US10773450

申请日：2004-12-02

Applicant: Chen-Chih Huang ,  Pao-Cheng Chiu

Inventor： Chen-Chih Huang ,  Pao-Cheng Chiu

IPC: H03H11/16

CPC classification number: H03K5/088 ,  H03K5/13 ,  H03K2005/00286

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract translation: 本发明涉及一种应用相位插值电路的相位插值电路和相位插值信号产生电路。 相位插补电路可以有效地避免短路电流。 此外，可以在时钟脉冲的上升沿和下降沿之间插入相间信号。 相位插值信号发生装置可以产生不仅具有线性分布相位而且维持多相时钟信号的良好的50％占空比的多相时钟信号。