公开(公告)号：US4855743A

公开(公告)日：1989-08-08

申请号：US130840

申请日：1987-12-09

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： G06F3/05

CPC分类号： G06F3/05

摘要： An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

摘要翻译： 模拟接口系统与数字信号处理器接口。 系统接收模拟信号，对这些信号进行数字化，并在完成转换后将其传输到信号处理器。 系统将数字数据从信号处理器传输到系统，并将其转换为模拟信号作为系统的输出。 响应于从信号处理器接收的数据，系统控制器选择A到D和D到A的转换速率。

公开(公告)号：US4803462A

公开(公告)日：1989-02-07

申请号：US84276

申请日：1987-08-11

申请人： Richard K. Hester ,  Michiel de Wit

发明人： Richard K. Hester ,  Michiel de Wit

IPC分类号： H03M1/02 ,  H03M1/00 ,  H03M1/38

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/804

摘要： An A/D converter includes a positive array of binary weighted capacitors with a common top plate (12) and a negative array of binary weighted capacitors with a common top plate (32). The positive and negative arrays are input to a differential amplifier (10) for measuring the differential voltage across the top plates. During the sample time, a differential input voltage is sampled on the bottom plates of the capacitors and the top plates of the capacitors are disposed at the common mode voltage of the input signal. This limits the input voltage across the capacitors to one-half the differential voltages of the input signal. During the hold mode and the redistribution mode, this presents a predetermined common mode input voltage to the amplifier (10) which is independent of the input signal.

摘要翻译： A / D转换器包括具有公共顶板（12）的二进制加权电容器的正阵列和具有公共顶板（32）的二进制加权电容器的负阵列。 正和负阵列被输入到差分放大器（10），用于测量跨越顶板的差分电压。 在采样时间期间，在电容器的底板上采样差分输入电压，并且电容器的顶板设置在输入信号的共模电压。 这将电容器两端的输入电压限制为输入信号差分电压的一半。 在保持模式和再分配模式期间，这给予与输入信号无关的放大器（10）的预定共模输入电压。

公开(公告)号：US08749215B2

公开(公告)日：2014-06-10

申请号：US12872831

申请日：2010-08-31

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： G05F1/00 ,  H02M3/158 ,  H02M1/14

CPC分类号： H02M1/14 ,  H02M3/1582

摘要： Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge that reduces ripple current or variations in the inductor current by adjusting phase relationships between corresponding buck and boost switches in a bridge or buck-boost mode.

摘要翻译： 传统上，由于它们无法在降压模式和升压模式之间无缝转换，因此避免了具有桥接拓扑的降压 - 升压开关稳压器。 然而，这里提供了具有桥接拓扑的降压 - 升压开关稳压器，其具有改进的控制器。 也就是说，处理器（例如数字信号处理器或DSP）为桥提供数字控制，通过调节桥或降压 - 升压模式中对应的降压和升压开关之间的相位关系，可减少纹波电流或电感电流变化。

公开(公告)号：US4831381A

公开(公告)日：1989-05-16

申请号：US084277

申请日：1987-08-11

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： H03M1/44 ,  H03M1/38 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/468 ,  H03M1/804

摘要： An A/D converter utilizing a charge redistribution scheme includes a single ended comparator and associated therewith a capacitor array of binary weighted capacitors. The input signal is sampled with the input of the comparator disposed at a point midway between ground and a unipolar reference voltage. The bottom plates of the capacitors in the hold mode are then disposed at the midpoint of the reference signal. In the redistribution mode, the value of the bits is determined by switching the bottom plates of the capacitors between the midpoint of the reference voltage and either ground or the full value of the reference voltage. The input signal during sampling is attenuated by sampling it onto only one-half of the array.

摘要翻译： 利用电荷再分配方案的A / D转换器包括单端比较器并与其相关联的二进制加权电容器的电容器阵列。 输入信号被采样，比较器的输入设置在地之间的中点和单极参考电压之间。 然后将保持模式中的电容器的底板设置在参考信号的中点。 在再分配模式下，通过在参考电压的中点与基准电压或参考电压的全部值之间切换电容器的底板来确定位的值。 采样期间的输入信号通过将其采样到阵列的一半来衰减。

公开(公告)号：US20120049818A1

公开(公告)日：2012-03-01

申请号：US12872896

申请日：2010-08-31

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： G05F1/10

CPC分类号： H02M3/1582 ,  Y10T307/50

摘要： Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.

摘要翻译： 传统上，由于它们无法在降压模式和升压模式之间无缝转换，因此避免了具有桥接拓扑的降压 - 升压开关稳压器。 然而，这里提供了具有桥接拓扑的降压 - 升压开关稳压器，其具有改进的控制器。 也就是说，处理器（例如数字信号处理器或DSP）为桥提供数字控制，使得它能够在降压模式和升压模式之间基本上无缝地转换。

公开(公告)号：US20120049816A1

公开(公告)日：2012-03-01

申请号：US12872831

申请日：2010-08-31

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： G05F1/10

CPC分类号： H02M1/14 ,  H02M3/1582

摘要： Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge that reduces ripple current or variations in the inductor current by adjusting phase relationships between corresponding buck and boost switches in a bridge or buck-boost mode.

摘要翻译： 传统上，由于它们无法在降压模式和升压模式之间无缝转换，因此避免了具有桥接拓扑的降压 - 升压开关稳压器。 然而，这里提供了具有桥接拓扑的降压 - 升压开关稳压器，其具有改进的控制器。 也就是说，处理器（例如数字信号处理器或DSP）为桥提供数字控制，通过调节桥或降压 - 升压模式中对应的降压和升压开关之间的相位关系，可减少纹波电流或电感电流变化。

公开(公告)号：US08013677B2

公开(公告)日：2011-09-06

申请号：US12639712

申请日：2009-12-16

申请人： Cetin Kaya ,  Richard K. Hester

发明人： Cetin Kaya ,  Richard K. Hester

IPC分类号： H03F3/217

CPC分类号： H03F3/2173 ,  H03F3/3022 ,  H03F3/45475 ,  H03F2203/45528 ,  H03F2203/45712

摘要： One-sided pulse width modulated (PWM) amplifiers are disclosed. An example amplifier includes an integrator to receive first and second analog signals, and to output a first amplified signal and a second amplified signal based on the first and second analog signals, a reference changer coupled to the integrator to determine whether a first amplitude is higher than a second amplitude based on the first and second analog signals, to selectively cause the integrator to apply a first resistance between a reference node and the first amplified signal and apply a second resistance between the reference node and the second amplified signal when the first amplitude is higher than the second amplitude, and to selectively cause the integrator to apply the second resistance between the reference node and the first amplified signal and apply the first resistance between the reference node and the second amplified signal when the second amplitude is higher than the first amplitude, and first and second comparators coupled to the integrator to receive the first and second amplified signals, to compare the first and second amplified signals to a reference signal, and to output first and second pulse width modulated signals having respective first and second pulse widths based on the comparisons between the first and second amplified signals and the reference signal.

摘要翻译： 公开了单侧脉宽调制（PWM）放大器。 示例放大器包括用于接收第一和第二模拟信号的积分器，并且基于第一和第二模拟信号输出第一放大信号和第二放大信号;耦合到积分器的参考变换器，以确定第一幅度是否更高 基于第一和第二模拟信号的第二幅度，选择性地使积分器在参考节点和第一放大信号之间施加第一电阻，并且当第一幅度在参考节点和第二放大信号之间施加第二电阻时 高于第二幅度，并且选择性地使积分器在参考节点和第一放大信号之间施加第二电阻，并且当第二幅度高于第一幅度时，将第一电阻施加在参考节点和第二放大信号之间 幅度以及耦合到积分器的第一和第二比较器以接收第一比较器 和第二放大信号，以将第一和第二放大信号与参考信号进行比较，并且基于第一和第二放大信号与参考信号之间的比较，输出具有各自的第一和第二脉冲宽度的第一和第二脉冲宽度调制信号 。

公开(公告)号：US06803811B2

公开(公告)日：2004-10-12

申请号：US10280398

申请日：2002-10-26

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： H03B100

CPC分类号： H03H7/48

摘要： A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.

公开(公告)号：US5920275A

公开(公告)日：1999-07-06

申请号：US925631

申请日：1997-09-09

申请人： Richard K. Hester

发明人： Richard K. Hester

IPC分类号： H03M1/20 ,  H03M1/46 ,  H03M1/14

CPC分类号： H03M1/206 ,  H03M1/468

摘要： A charge redistribution analog-to-digital converter uses an interpolative comparator to determine multiple bits in a single comparator decision cycle. The result is a speed improvement in the conversion period with little or no increase in power dissipation.

摘要翻译： 电荷再分配模数转换器使用内插比较器来确定单个比较器决策周期中的多个比特。 结果是转换周期的速度提高，功耗很少或没有增加。

公开(公告)号：US4975700A

公开(公告)日：1990-12-04

申请号：US497809

申请日：1990-03-21

申请人： Khen-Sang Tan ,  Richard K. Hester ,  John W. Fattaruso

发明人： Khen-Sang Tan ,  Richard K. Hester ,  John W. Fattaruso

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/0612 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/804

摘要： An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

摘要翻译： 公开了一种提供纠错的模数转换器和方法，其消除了通过电容器值依赖于电压而产生的线性和二次误差项。