公开(公告)号：US4975700A

公开(公告)日：1990-12-04

申请号：US497809

申请日：1990-03-21

申请人： Khen-Sang Tan ,  Richard K. Hester ,  John W. Fattaruso

发明人： Khen-Sang Tan ,  Richard K. Hester ,  John W. Fattaruso

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/0612 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/804

摘要： An analog-to-digital converter and method which provides error correction is disclosed that eliminates the linear and quadratic error terms which arise through capacitor value dependence upon voltage.

摘要翻译： 公开了一种提供纠错的模数转换器和方法，其消除了通过电容器值依赖于电压而产生的线性和二次误差项。

公开(公告)号：US5248974A

公开(公告)日：1993-09-28

申请号：US722731

申请日：1991-06-27

申请人： John W. Fattaruso ,  Khen-Sang Tan

发明人： John W. Fattaruso ,  Khen-Sang Tan

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/44 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/0607 ,  H03M1/468 ,  H03M1/804

摘要： This dielectric relaxation correction circuit for charge-redistribution A/D converters, which has a comparator 20 and operates in a sample, hold and conversion mode, comprises: a capacitor array 22, a replica capacitance 35, having a bottom plate, arranged so as to be subject to the same sequence of charging voltages that the array capacitors 22 experience but in a neutralizing manner such that an error in the capacitor array 22 voltage is neutralized by the same error in the replica capacitance 35, and; a sample and hold circuit (S/H) 36 for sampling an input signal voltage during the sample mode, wherein the sample and hold 36 is arranged to hold the bottom plate of the replica capacitance 35 at the input signal voltage. Other devices, systems and methods are also disclosed.

公开(公告)号：US4638451A

公开(公告)日：1987-01-20

申请号：US491140

申请日：1983-05-03

申请人： Richard K. Hester ,  Khen-Sang Tan

发明人： Richard K. Hester ,  Khen-Sang Tan

IPC分类号： G06F3/05 ,  G06F3/16 ,  G06F13/00

CPC分类号： G06F3/05 ,  G06F3/16

摘要： A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.

摘要翻译： 微处理器系统包括具有片上或片外存储器的CPU装置以及用于访问存储器和/或外围设备的数据和控制总线。 外围电路包括用于输入和/或输出数据的一个或多个通道，其中通道中数据处理的各种特性由在CPU中执行的程序控制。 在一个实施例中，包括模拟输入和输出通道，并且通过执行CPU的数据输出指令来选择A到D或D到A的转换速率。 同样选择过滤器的截止点。 A到D转换器加载先进先出的存储器，当CPU被填充时，它以突发模式读取。 同样，CPU将数字数据加载到输出通道中的先进先出存储器，然后D到A以其选定的速率转换。

公开(公告)号：US5235335A

公开(公告)日：1993-08-10

申请号：US892447

申请日：1992-06-02

申请人： Richard K. Hester ,  Khen-Sang Tan ,  Michiel de Wit

发明人： Richard K. Hester ,  Khen-Sang Tan ,  Michiel de Wit

IPC分类号： H03M1/10 ,  H03M1/80

CPC分类号： H03M1/1033 ,  H03M1/804

摘要： A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.CAL comprises array 26 of calibration capacitors 28a-28n, each associated with a switch element 30a- 30n. The array 26 may be a binary weighted array.

摘要翻译： 本文公开了一种电容器阵列电路。 主电容器阵列至少包括最有效的阵列部分12和最不重要的阵列部分14.耦合电容器CC形成在阵列的两个部分之间。 通常，耦合电容器CC的一个板耦合到最不重要的阵列部分14中的每个电容器的顶板，并且耦合电容器CC的第二板最多地耦合到每个电容器的顶板 还提供可变校准电容器CCAL。 在优选实施例中，可变校准电容器CCAL耦合在耦合电容器CC和AC接地节点之间。 在替代实施例中，可变校准电容器CCAL与耦合电容器CC并联耦合。 在优选实施例中，可变校准电容器CCAL包括校准电容器28a-28n的阵列26，每个与开关元件30a-30n相关联。 阵列26可以是二进制加权阵列。

公开(公告)号：US5353028A

公开(公告)日：1994-10-04

申请号：US882775

申请日：1992-05-14

申请人： Michiel de Wit ,  Khen-Sang Tan

发明人： Michiel de Wit ,  Khen-Sang Tan

IPC分类号： H03K19/177 ,  G05F3/26 ,  H03M1/10 ,  H03M1/46 ,  H03M1/80 ,  H03M1/38

CPC分类号： G05F3/262 ,  H03M1/1009 ,  H03M1/466 ,  H03M1/804

摘要： A differential fuse circuit 10 is disclosed herein. A first fuse 12 and a second fuse 14 are coupled to a supply potential V.sub.DD (e.g., five volts). Circuitry 16 and 18 for blowing the two fuses 12 and 14 is also provided. A current mirror 46 including a first leg and a second leg is also provided. The current mirror 46 is designed so that a current through the first leg will induce a current in the second leg. The first leg is coupled between the first fuse 12 and a reference potential V.sub.SS and the second leg is coupled between the second fuse 14 and the reference potential V.sub.SS. An output node 56 is provided between the second fuse 14 and the second leg of the current mirror 46. A differential sense circuit 24 may also be included between the fuses 12 and 14 and the current mirror 46. During operation, the output node is at a potential substantially near the reference potential when the first fuse has a resistance greater than the second fuse and the output node is at a potential substantially near the supply potential when the first fuse has a resistance less than the second fuse. Other systems and methods are also disclosed.

摘要翻译： 本文公开了差分熔丝电路10。 第一熔丝12和第二熔丝14耦合到电源电位VDD（例如，五伏特）。 还提供了用于吹制两个保险丝12和14的电路16和18。 还提供了包括第一腿部和第二腿部的电流镜46。 电流镜46被设计成使得通过第一支腿的电流将引起第二支路中的电流。 第一支路耦合在第一保险丝12和基准电位VSS之间，第二支路耦合在第二保险丝14和基准电位VSS之间。 输出节点56设置在第二熔断器14和电流镜46的第二支路之间。差分感测电路24也可以包括在保险丝12和14与电流镜46之间。在操作期间，输出节点处于 当第一保险丝的电阻大于第二保险丝时，第一保险丝的电阻基本上接近于参考电位，并且当第一保险丝的电阻小于第二保险丝时，输出节点处于基本上接近电源电位的电位。 还公开了其它系统和方法。

公开(公告)号：US4399426A

公开(公告)日：1983-08-16

申请号：US260435

申请日：1981-05-04

申请人： Khen-Sang Tan

发明人： Khen-Sang Tan

IPC分类号： H03M1/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/38 ,  H03K13/02

CPC分类号： H03M1/1023 ,  H03M1/183

摘要： A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.

摘要翻译： 公开了一种校正数据采集系统中产生的错误的方法和装置。 公开了一种用于在电荷再分配，加权电容阵列模数转换器中校正诸如二进制加权电容器和偏移之间的误差的误差的方法和电路。 自校准的自校正电路由电容器的第二二进制阵列组成，其增加了常规电荷再分配电容器阵列的纠错信号以补偿失配。 然后存储该纠错信号，并确定常规电容器阵列中的其它电容器的其他纠错信号，并随后存储以用于其他电容失配的稍后校正。

公开(公告)号：US5006853A

公开(公告)日：1991-04-09

申请号：US478596

申请日：1990-02-12

申请人： Sami Kiriaki ,  Khen-Sang Tan

发明人： Sami Kiriaki ,  Khen-Sang Tan

IPC分类号： H03M1/10 ,  H03M1/14 ,  H03M1/38 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/14 ,  H03M1/468 ,  H03M1/804

摘要： An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators. The voltage shift as a result of this hysteresis is not a significant factor for the bits generated by the coarse comparator and as such the system (10) may accomplish high resolution analog to digital conversions.

摘要翻译： 公开了一种模数转换器系统（10），其包括控制电容阵列控制开关（14）的SAR逻辑电路（12），其自身控制电容器阵列（16）。 电容器阵列（18）的顶板（18）选择性地耦合到粗略比较器（24）和精细比较器（26）。 粗略比较器（24）和精细比较器（26）的输出被输入到纠错电路（28）中。 在操作中，粗略比较器（24）用于近似由系统（10）输出的数字字的预定数量的最高有效位，而精细比较器（26）用于近似该数字字的剩余位 数字词 以这种方式，粗略比较器（24）单独受到可能导致误差的高电压，作为用于构建比较器的MOSFET的阈值电压中的滞后效应的结果。 作为这种滞后的结果的电压偏移不是由粗略比较器产生的位的重要因素，并且因此系统（10）可以实现高分辨率模数转换。

公开(公告)号：US5338897A

公开(公告)日：1994-08-16

申请号：US738010

申请日：1991-07-30

申请人： Ching-Yuh Tsay ,  Khen-Sang Tan

发明人： Ching-Yuh Tsay ,  Khen-Sang Tan

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L23/58 ,  H01L27/108 ,  H01P3/06 ,  H03K17/16 ,  H05K9/00

CPC分类号： H01L27/108 ,  H01L23/585 ,  H01L2223/6622 ,  H01L2924/0002

摘要： In a semiconductor device, an on chip coaxial cable reduces noise from adversely affecting a signal transmitted by a signal conductor. The signal conductor lies within and is isolated from a second conductor. A dielectric, such as oxide, may provide isolation. In multi level metal devices, such as double level metal devices, the signal conductor can be formed of a first level of metal and a portion of the second conductor can be formed of the first level of metal also. After forming a first level of metal, it is patterned to separate the first signal conductor from a first conductive noise shield and a second conductive noise shield. A second level of metal and a conductive level of material such as polysilicon can complete formation of the second conductor. Oxide insulators can provide isolation between the signal conductor and the second conductor by lying between the top conductive noise shield and the signal conductor and by lying between the bottom conductive noise shield and the signal conductor. Interlevel connectors such as vias and contacts in the oxide insulators provide electrical coupling between the various levels of the second conductor. A signal carrier is centered inside and insulated from an outer conductor on a semiconductor chip and provides an on chip coaxial cable that protects the signal carrier from noise disturbances. The second conductor may be electrically biased, such as to ground, by connecting the bottom conductive noise shield to a voltage source to enhance noise reduction.

摘要翻译： 在半导体器件中，片上同轴电缆降低噪声，从而不利地影响由信号导体传输的信号。 信号导体位于第二导体内并与第二导体隔离。 诸如氧化物的电介质可以提供隔离。 在诸如双层金属器件的多级金属器件中，信号导体可以由第一级金属形成，并且第二导体的一部分也可以由第一级金属形成。 在形成第一级金属之后，图案化以将第一信号导体与第一导电噪声屏蔽和第二导电噪声屏蔽分开。 第二级金属和诸如多晶硅的材料的导电水平可以完成第二导体的形成。 氧化物绝缘体可以通过位于顶部导电噪声屏蔽和信号导体之间并通过位于底部导电噪声屏蔽和信号导体之间来提供信号导体与第二导体之间的隔离。 诸如通孔和氧化物绝缘体中的触点的层间连接器提供第二导体的各个电平之间的电耦合。 信号载体位于半导体芯片的内部并与外部导体绝缘，并提供一种片上同轴电缆，保护信号载波免受噪声干扰。 第二导体可以通过将底部导电噪声屏蔽件连接到电压源而被电偏置，例如接地，以增强降噪。

公开(公告)号：US4989002A

公开(公告)日：1991-01-29

申请号：US478312

申请日：1990-02-12

申请人： Khen-Sang Tan

发明人： Khen-Sang Tan

IPC分类号： H03M1/06 ,  H03M1/10 ,  H03M1/80

CPC分类号： H03M1/0682 ,  H03M1/1052 ,  H03M1/804

摘要： There is disclosed a fully differential converter (10) having a very high common mode rejection ratio. The capacitive parasitics (CP) are accounted for by a strategic placement of error correction capacitances (20). The actual value of the capacitance is calculated from time to time by successively making comparative circuit operations and by adding and subtracting capacitance automatically under logic control (62) until the circuit is in near balance. The final value of the added capacitance for any given calculation set is stored in a memory (61). In this manner the circuit become self-calibrating and common mode rejection ratios over 90 db are possible.

摘要翻译： 公开了具有非常高的共模抑制比的全差分转换器（10）。 电容寄生率（CP）由误差补偿电容的策略位置（20）来解释。 电容的实际值通过连续进行比较电路操作，并在逻辑控制（62）下自动加减电容直到电路接近平衡来计算。 任何给定计算集合的附加电容的最终值存储在存储器（61）中。 以这种方式，电路变为自校准，并且90db以上的共模抑制比是可能的。

公开(公告)号：US4654815A

公开(公告)日：1987-03-31

申请号：US699516

申请日：1985-02-07

申请人： James S. Marin ,  Khen-Sang Tan

发明人： James S. Marin ,  Khen-Sang Tan

IPC分类号： G06J1/00 ,  H03M1/00

CPC分类号： G06J1/00 ,  H03M1/1047

摘要： An analog signal conditioning and digitizing integrated circuit is provided having a multiplying digital to analog converter means (MDAC) including a gain capacitor array and an offset capacitor array, an operational amplifier, a feedback circuit including a feedback capacitor and a feedback clamping transistor, the operational amplifier and feedback circuit connected to the gain and offset capacitor arrays for setting the gain and the amount of offset correction of the MDAC, a correlated double sample circuit including a series capacitor connected to the operational amplifier and a series clamping transistor connected to the junction of the series capacitor and a buffer amplifier for sampling the noise to be substracted and/or nulled across the series capacitor, and an analog to digital converter operatively connected to the MDAC for digitizing the output of the MDAC. In other embodiments the integrated circuit has separate bond pads for the analog signal inputs and outputs of the MDACs and DACs or for implementing feedback/feedforward discrete time transfer functions.

摘要翻译： 提供了一种模拟信号调理和数字化集成电路，其具有包括增益电容器阵列和偏移电容器阵列的乘法数模转换器装置（MDAC），运算放大器，包括反馈电容器和反馈钳位晶体管的反馈电路， 连接到增益和偏移电容器阵列的运算放大器和反馈电路，用于设置MDAC的增益和偏移校正量，包括连接到运算放大器的串联电容器的相关双采样电路和连接到运算放大器的串联钳位晶体管 串联电容器的缓冲放大器和用于对串联电容器之间被减法和/或零化的噪声进行采样的缓冲放大器，以及可操作地连接到MDAC的模数转换器，用于数字化MDAC的输出。 在其他实施例中，集成电路具有用于MDAC和DAC的模拟信号输入和输出的单独接合焊盘或用于实现反馈/前馈离散时间传递函数。