公开(公告)号：USRE35951E

公开(公告)日：1998-11-10

申请号：US266961

申请日：1994-06-27

申请人： Apparajan Ganesan ,  Robert J. Libert

发明人： Apparajan Ganesan ,  Robert J. Libert

IPC分类号： G05F3/20 ,  G05F3/30 ,  H03K5/08 ,  G05F3/24

CPC分类号： G05F3/30 ,  G05F3/20

摘要： A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.

摘要翻译： 构成CMOS IC芯片的一部分的带隙电压基准。 DELTA VBE电压由堆叠的寄生双极晶体管对开发，每对晶体管以不同的电流密度工作。 MOS缓冲晶体管连接在其中开发DELTA VBE电压的堆叠的相应端。 双极晶体管由MOS电流源驱动。

公开(公告)号：US5550486A

公开(公告)日：1996-08-27

申请号：US396849

申请日：1995-03-01

申请人： Frank J. Sweeney ,  Apparajan Ganesan

发明人： Frank J. Sweeney ,  Apparajan Ganesan

IPC分类号： H03K19/003 ,  H03K19/007 ,  H03K17/16

CPC分类号： H03K19/00315 ,  H03K19/007

摘要： A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130). In one embodiment (120), the MOS state controlling transistor (124) is an NMOS transistor and the MOS logic transistor (122) is a PMOS transistor.

摘要翻译： 当逻辑电路的电源电压上升到预定电平以上时，将逻辑电路的输出强制为已知状态的电路和方法包括连接在电源电压（129）和输出线（130）之间的MOS逻辑晶体管（122）并连接 以在其门上接收输入信号（126）。 与MOS逻辑晶体管（122）相反导电类型的MOS状态控制晶体管（124）连接在输出线（130）和基准电位（-Vss）之间，其栅极连接到MOS逻辑晶体管 （122）。 电源（132）连接在电源电压（128）和MOS状态控制晶体管（124）的栅极之间。 如果电源电压（128）上升到由MOS状态控制晶体管的阈值电压建立的预定电平以上，则MOS状态控制晶体管（124）导通，以在输出线（130）上产生参考电位。 在一个实施例（120）中，MOS状态控制晶体管（124）是NMOS晶体管，MOS逻辑晶体管（122）是PMOS晶体管。

公开(公告)号：US4544878A

公开(公告)日：1985-10-01

申请号：US538946

申请日：1983-10-04

申请人： Richard G. Beale ,  Apparajan Ganesan

发明人： Richard G. Beale ,  Apparajan Ganesan

IPC分类号： G05F3/24 ,  G05F3/26 ,  H03K17/687 ,  G05F3/20

CPC分类号： G05F3/262

摘要： The input (16) and output (20) MOS transistors of a current mirror (10) have their sources connected to a supply voltage node (12). The gate of the input transistor (16) is connected to its drain and is also connected to the gate of the output transistor (20) through an isolation switch (24). The gate of the output transistor (20) is connected to the supply voltage node (12) through a disable switch (26). Closing of the disable switch (26) and opening of the isolation switch (24) turns off current in the output transistor (20). Opening the disable switch (26) and closing the isolation switch (24) turns the output current on again.Also disclosed is a mirror (28) having switches (30), (32) configured for various logic functions. A voltage-controlled oscillator (34) and a phase detector circuit 72 having a switched current input provided by switched current mirrors (40, 42, 80, 82) is described.

摘要翻译： 电流镜（10）的输入（16）和输出（20）MOS晶体管的源极连接到电源电压节点（12）。 输入晶体管（16）的栅极连接到其漏极，并且还通过隔离开关（24）连接到输出晶体管（20）的栅极。 输出晶体管（20）的栅极通过禁止开关（26）连接到电源电压节点（12）。 禁止开关（26）的闭合和隔离开关（24）的断开使得输出晶体管（20）中的电流截止。 打开禁用开关（26）并关闭隔离开关（24）将再次打开输出电流。 还公开了具有被配置用于各种逻辑功能的开关（30），（32）的反射镜（28）。 描述了具有由开关电流镜（40,42,80,82）提供的开关电流输入的压控振荡器（34）和相位检测器电路72。

公开(公告)号：US20070036299A1

公开(公告)日：2007-02-15

申请号：US11184246

申请日：2005-07-20

申请人： Douglas Marsh ,  Apparajan Ganesan

发明人： Douglas Marsh ,  Apparajan Ganesan

IPC分类号： H04M1/64

CPC分类号： G06Q10/109 ,  H04M1/72566

摘要： In accordance with the present invention, a reminder service is disclosed that uses computer-like means to store information regarding the action being reminded. The service allows either the service provider or the end user to define the relevant information, that is, the what of the reminder, the when to do the reminding, the how and where to transmit the reminder, and the form of the reminder.

摘要翻译： 根据本发明，公开了一种提醒服务，其使用类似计算机的方式来存储关于要提醒的动作的信息。 该服务允许服务提供商或最终用户定义相关信息，即提醒的内容，何时进行提醒，如何以及在哪里传送提醒，以及提醒的形式。

公开(公告)号：US20070018318A1

公开(公告)日：2007-01-25

申请号：US11184220

申请日：2005-07-20

申请人： Douglas Marsh ,  Apparajan Ganesan

发明人： Douglas Marsh ,  Apparajan Ganesan

IPC分类号： H01L23/48

CPC分类号： H04R19/04 ,  H01L2924/0002 ,  H04R19/005 ,  H01L2924/00

摘要： A means of integrating a microphone on the same integrated circuit die as other electronics in the system is disclosed. The structure is based on using solder bump technology to form a gap between an electrode on the silicon and another electrode. Charge is stored on the capacitor so when pressure from sound waves causes one electrode to flex, the capacitance and therefore the charge changes, causing signal current.

摘要翻译： 公开了将麦克风与系统中的其他电子设备集成在同一集成电路管芯上的方法。 该结构基于使用焊料凸块技术在硅上的电极和另一个电极之间形成间隙。 电荷存储在电容器上，因此当声波的压力导致一个电极弯曲时，电容和电荷变化，导致信号电流。

公开(公告)号：US06864741B2

公开(公告)日：2005-03-08

申请号：US10314470

申请日：2002-12-09

申请人： Douglas G. Marsh ,  Apparajan Ganesan

发明人： Douglas G. Marsh ,  Apparajan Ganesan

IPC分类号： G05F3/30 ,  G05F1/10

CPC分类号： G05F3/30

摘要： The junction difference used for a band gap voltage reference is designed so that it has the needed temperature coefficient without amplification. This is accomplished by the appropriate choice of the number of junctions and the appropriate current densities. Only one polarity of bipolar transistors is required. The noise terms of each junction add in root mean square, rather than be linear amplification, resulting in a lower noise reference than other designs requiring only a single type of bipolar transistors. By using metal available in standard integrated circuit processes to form a resistor, a low temperature coefficient current source can easily be obtained.

摘要翻译： 用于带隙电压基准的结差设计成使其具有不需要放大的所需温度系数。 这是通过适当选择接点数量和适当的电流密度来实现的。 只需要双极晶体管的一个极性。 每个结点的噪声项加上均方根，而不是线性放大，导致比仅需要单一类型双极晶体管的其他设计更低的噪声参考值。 通过使用在标准集成电路工艺中可用的金属来形成电阻器，可以容易地获得低温度系数电流源。

公开(公告)号：US5404172A

公开(公告)日：1995-04-04

申请号：US845734

申请日：1992-03-02

申请人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

发明人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

IPC分类号： H03K5/007 ,  H03K5/08 ,  H04L7/10 ,  H04L25/06 ,  H04N5/08 ,  H04N5/445 ,  H04N7/035 ,  H04N7/087

CPC分类号： H04L25/062 ,  H03K5/007 ,  H03K5/082 ,  H04N5/08 ,  H04N5/44504 ,  H04N7/035 ,  H04N7/0352 ,  H04L7/10

摘要： A data and synchronization extraction circuit for processing composite video signals containing closed captioning data is disclosed. A dual mode voltage clamp is realized in CMOS technology which includes temperature compensated current sources in the form of complementary current mirrors. A modified version of such current sources is also disclosed which permits trimming of the current after manufacture and packaging. Sync pulses are separated by doubling the amplitude of a composite video signal with an amplifier and comparing the amplified signal with a back porch level derived by a sample-and-hold device. Frequency and phase synchronization is accomplished by a combination of a frequency lock loop and a phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator provides a clean source of timing information for the circuit. The effects of impulse noise in the detection of vertical retrace pulses are eliminated by the use of digital counting circuits which count the requisite number of horizontal synchronization pluses which occur between valid retrace pulse and which block pluses that appear at other times. A slice level for a data line is held by a small on-chip capacitor. Said slice level is periodically encoded. A decoder converts the encoded level back to an analog format during desired intervals.

摘要翻译： 公开了一种用于处理包含隐藏字幕数据的复合视频信号的数据和同步提取电路。 CMOS模式实现了双模电压钳位，其中包括补偿电流镜形式的温度补偿电流源。 还公开了这种电流源的修改版本，其允许在制造和封装之后修整电流。 通过用放大器将复合视频信号的振幅加倍来分离同步脉冲，并将放大的信号与由采样和保持设备导出的后沿电平进行比较。 频率和相位同步通过频率锁定环和相位锁相环的组合来实现，以在飞轮模式下产生用于压控振荡器的控制电压。 压控振荡器为电路提供了清晰的定时信息源。 通过使用数字计数电路来消除脉冲噪声对垂直回扫脉冲检测的影响，数字计数电路计算在有效回扫脉冲与其他时间出现的阻塞脉冲之间发生的水平同步脉冲的必要数量。 数据线的限幅电平由小的片上电容器保持。 所述切片级别被周期性地编码。 解码器将所编码的级别在期望的间隔期间转换为模拟格式。

公开(公告)号：US07317234B2

公开(公告)日：2008-01-08

申请号：US11184220

申请日：2005-07-20

申请人： Douglas G Marsh ,  Apparajan Ganesan

发明人： Douglas G Marsh ,  Apparajan Ganesan

IPC分类号： H01L29/84

CPC分类号： H04R19/04 ,  H01L2924/0002 ,  H04R19/005 ,  H01L2924/00

摘要： A means of integrating a microphone on the same integrated circuit die as other electronics in the system is disclosed. The structure uses solder bump technology to form a gap between an electrode on the silicon and another electrode. Charge is stored on the capacitor so when pressure from sound waves causes one electrode to flex, the capacitance and therefore the charge changes, causing signal current. The structure allows for area efficiency by allowing placement of active silicon circuitry under the microphone.

摘要翻译： 公开了将麦克风与系统中的其他电子设备集成在同一集成电路管芯上的方法。 该结构使用焊料凸点技术在硅上的电极和另一个电极之间形成间隙。 电荷存储在电容器上，因此当声波的压力导致一个电极弯曲时，电容和电荷变化，导致信号电流。 该结构通过允许将有源硅电路放置在麦克风之下来实现区域效率。

公开(公告)号：US20050205408A1

公开(公告)日：2005-09-22

申请号：US10805506

申请日：2004-03-22

申请人： Douglas Marsh ,  Apparajan Ganesan

发明人： Douglas Marsh ,  Apparajan Ganesan

IPC分类号： B01D3/10 ,  C02F1/04 ,  C02F1/32 ,  C02F1/467 ,  F03D9/00

CPC分类号： C02F1/047 ,  C02F1/32 ,  C02F1/4674 ,  C02F2103/08 ,  C02F2201/009 ,  F03D9/00 ,  F05B2220/62 ,  Y02A20/128 ,  Y02A20/141 ,  Y02A20/211 ,  Y02A20/212 ,  Y02E10/72

摘要： In accordance with the present invention, a conventional wind turbine used to generate electricity is modified to have a transparent roof, the roof being constructed in a way similar to seawater distillation plants. A small portion of the electricity generated by wind turbines is used to pump unpurified water to the roof of the generation system where it is distilled into pure drinking water. This water can then be gravity fed or pumped, again using the electricity from the turbine, elsewhere for storage and eventual use. Periodically, the purification process can be shut down and either purified or unpurified water can be used to flush the pollutants back to the water source and to clean the outside of the roof, and energy needed for these operations is also obtained from the electricity generated by the turbines. The system provides a means of adding to the purity of the water by killing bacteria with ultra-violate radiation and a means of storing excess wind generated electricity in the form of potable water.

摘要翻译： 根据本发明，用于发电的常规风力涡轮机被修改为具有透明屋顶，屋顶以类似于海水蒸馏设备的方式构造。 风力涡轮机产生的一小部分电力用于将未净化的水泵送到发电系统的屋顶，将其蒸馏成纯净的饮用水。 然后可以将水重力进给或泵送，再次使用来自涡轮机的电力，在其他地方储存和最终使用。 周期性地，可以关闭净化过程，并且可以使用纯化或未纯化的水将污染物冲洗回水源并清洁屋顶外部，并且这些操作所需的能量也可以从由 涡轮机。 该系统提供了一种通过杀死具有超临界辐射的细菌来增加水的纯度的手段，并且以饮用水的形式存储过量的风发电。

公开(公告)号：US5126653A

公开(公告)日：1992-06-30

申请号：US590655

申请日：1990-09-28

申请人： Apparajan Ganesan ,  Robert J. Libert

发明人： Apparajan Ganesan ,  Robert J. Libert

IPC分类号： G05F3/20 ,  G05F3/30 ,  H03K5/08

CPC分类号： G05F3/30 ,  G05F3/20

摘要： A band-gap voltage reference forming part of a CMOS IC chip. A .DELTA.V.sub.BE voltage is developed by stacked pairs of parasitic bipolar transistors, with the transistors of each pair operated at different current densities. MOS buffer transistors are connected at corresponding ends of the stacks where the .DELTA.V.sub.BE voltage is developed. The bipolar transistors are driven by MOS current sources.

摘要翻译： 构成CMOS IC芯片的一部分的带隙电压基准。 DELTA VBE电压由堆叠的寄生双极晶体管对开发，每对晶体管以不同的电流密度工作。 MOS缓冲晶体管连接在其中开发DELTA VBE电压的堆叠的相应端。 双极晶体管由MOS电流源驱动。