公开(公告)号：US20070120021A1

公开(公告)日：2007-05-31

申请号：US11271137

申请日：2005-11-11

申请人： Yu-Shen Lin ,  Ling-Xian Wang

发明人： Yu-Shen Lin ,  Ling-Xian Wang

IPC分类号： F16L3/00

CPC分类号： F16B2/18

摘要： The present invention relates to a hanging clamp for different size rods, which comprises a L-shaped base having a body, a rotatory piece capable of rotating at a predetermined angle, as well as a clamping member also capable of rotating at a predetermined angle; wherein a retaining portion projects out of one end of body, the rotatory piece is pivoted at a proper position of body by means of a first pivotal axis, while the clamping member is pivoted at one end of rotatory piece by using a second pivotal axis; furthermore, the clamping member in response to the retaining portion is provided with an arc-shaped clamping surface having a concentric circle, whereby enabling the rotatory piece pivotally rotate the clamping member to clamp different size rods, by using the changeable distance between the clamping surface and the retaining portion; prefectably, the clamping member can also pivotally rotate to increase or decrease said changeable distance between the clamping surface and the retaining portion, so as to expand the clamping size range of hanging clamp for different size rods by using the changeable distance of double pivotal axis.

摘要翻译： 本发明涉及一种用于不同尺寸的杆的悬挂夹具，其包括具有主体的L形基座，能够以预定角度旋转的旋转件以及还能够以预定角度旋转的夹紧构件; 其中，保持部从主体的一端伸出，所述旋转件通过第一枢转轴线在本体的适当位置枢转，同时所述夹紧构件通过使用第二枢转轴线在所述旋转件的一端枢转; 此外，夹持构件响应于保持部分设置有具有同心圆的弧形夹紧表面，由此通过使用夹紧表面之间的可变距离使得旋转件可枢转地旋转夹紧构件以夹紧不同尺寸的杆 和保持部分; 可靠地，夹紧构件还可以枢转地旋转以增加或减小夹紧表面和保持部分之间的可变距离，从而通过使用双枢转轴线的可变距离来扩大用于不同尺寸的杆的悬挂夹具的夹紧尺寸范围。

公开(公告)号：US20060164887A1

公开(公告)日：2006-07-27

申请号：US11043550

申请日：2005-01-26

申请人： Yu-Shen Lin ,  Hsien-Wen Hsu

发明人： Yu-Shen Lin ,  Hsien-Wen Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/349 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436

摘要： A nonvolatile memory array is associated with counting memory that stores data on a number of times a particular threshold state is reached in the associated nonvolatile memory. The aging physical characteristics of the nonvolatile memory can be compensated by adjusting the operating conditions of the nonvolatile memory. The operating conditions vary depending on the data stored in the counting memory.

摘要翻译： 非易失性存储器阵列与在相关联的非易失性存储器中达到特定阈值状态的次数存储数据的计数存储器相关联。 可以通过调整非易失性存储器的工作条件来补偿非易失性存储器的老化物理特性。 操作条件取决于存储在计数存储器中的数据。

公开(公告)号：US20060104098A1

公开(公告)日：2006-05-18

申请号：US11286204

申请日：2005-11-23

申请人： Lung-Yi Chueh ,  Yu-Shen Lin

发明人： Lung-Yi Chueh ,  Yu-Shen Lin

IPC分类号： H02M3/18

CPC分类号： H02M3/073 ,  H02M1/143 ,  H02M1/15 ,  H02M2003/075

摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.

摘要翻译： 公开了一种用于电荷泵的电压调节装置。 电荷泵根据至少一个时钟信号的工作输出输出电压。 电压调节装置至少包括一个电压调节电容器和至少一个逆变器。 逆变器用于接收时钟信号并相应地输出反相时钟信号。 电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。

公开(公告)号：US06496417B1

公开(公告)日：2002-12-17

申请号：US09601089

申请日：2000-07-27

申请人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Han Sung Chen ,  Yu-Shen Lin ,  Wen-Pin Lu ,  Tso-Ming Chang

发明人： Tzeng-Huei Shiau ,  Ray-Lin Wan ,  Han Sung Chen ,  Yu-Shen Lin ,  Wen-Pin Lu ,  Tso-Ming Chang

IPC分类号： G11C1604

CPC分类号： G11C16/107 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3445

摘要： A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.

摘要翻译： 用于在擦除之后执行软程序的方法和集成电路提供了布置在位线中的过擦除的浮动栅极存储单元的有效收敛。 软程序应用于连续的主题位线。 BLISP方法包括选择所选位线并将软程序应用于对应于所选位线的对象位线。 对于没有有缺陷的位线的集成电路，主题位线包括所选择的位线。 与批量软编程方法相比，BLISP方法适用于低电流消耗。 在一些实施例中，集成电路包括有缺陷的位线。 对于这些集成电路，选择的位线的选择包括指示对应于所选位线的位线类型。 有缺陷的位线在逻辑上被冗余位线替代，使得软程序被应用于对应于有缺陷位线的选定位线和冗余位线。 可以在软程序期间禁用第一存储器阵列中的有缺陷的位线，并且由位于第二存储器阵列中的对应的冗余位线替换第一存储器阵列中的有缺陷的位线，使得软程序不被施加到有缺陷的位线。 通过防止将软程序应用于有缺陷的位线，BLISP方法避免消耗过剩的电流，否则会由设置在有缺陷位线上的非常低的阈值电压存储单元消耗。 过度的电流将使软程序方法效率低得多。

公开(公告)号：US06229732B1

公开(公告)日：2001-05-08

申请号：US09380873

申请日：1999-09-09

申请人： Yu-Shen Lin ,  Tzeng-Huei Shiau ,  Ray-Lin Wan

发明人： Yu-Shen Lin ,  Tzeng-Huei Shiau ,  Ray-Lin Wan

IPC分类号： G11C1604

CPC分类号： G11C5/147 ,  G11C16/12 ,  G11C16/30

摘要： A circuit is provided for applying a negative voltage to the control gate of a floating gate memory cell and a positive voltage to the source drain or channel which comprises a positive voltage source to provide a positive voltage to the source of the cell, and a negative voltage source responsive to the supply voltage to provide a negative voltage to the control gate. A voltage regulator is included that is coupled to the negative voltage source and to the positive voltage source to maintain the negative voltage at a level responsive to the source voltage. The regulator maintains the negative voltage in response to the source voltage so that the electric field remains essentially constant over a range of values of source voltage.

摘要翻译： 提供电路用于向浮动栅极存储单元的控制栅极施加负电压，并向源极漏极或沟道施加正电压，该正电压包括正电压源以向电池源提供正电压，负电压 电压源响应于电源电压以向控制栅极提供负电压。 包括耦合到负电压源和正电压源的电压调节器，以将负电压保持在响应于电源电压的电平。 调节器响应于源极电压维持负电压，使得电源在源极电压值的范围内基本保持恒定。

公开(公告)号：US5966331A

公开(公告)日：1999-10-12

申请号：US122258

申请日：1998-07-24

申请人： Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Ray-Lin Wan

发明人： Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Ray-Lin Wan

IPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： The negative supply voltage and isolation well bias used by the drivers during sector or chip level erase operations are decoded separately from each other and from the decoding of the inputs of the individual wordline drivers in a compact wordline driver and decoder system. An integrated circuit memory comprising an array of memory cells arranged in a plurality of segments, a set of wordlines is coupled to the memory cells in the array, and wordline driver circuitry using shared isolation well MOS transistors coupled to the set of wordlines is provided. The wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source for the shared isolation well and a set of wordline drivers. The wordline drivers are coupled to the first, second and third supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors. Each supply voltage selector in the set is coupled with a subset of the set of drivers. The subset of drivers is coupled with a respective segment in the array. The supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments. The selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.

摘要翻译： 在扇区或芯片级擦除操作期间由驱动器使用的负电源电压和隔离阱偏压彼此分开解码，并且在紧凑的字线驱动器和解码器系统中对各个字线驱动器的输入进行解码。 一种集成电路存储器，包括布置在多个段中的存储单元的阵列，一组字线耦合到该阵列中的存储单元，并且提供了使用共享隔离阱MOS晶体管的字线驱动器电路，耦合到该组字线。 字线驱动器电路包括第一电源电压源，第二电源电压源，用于共用隔离阱的第三电源电压源和一组字线驱动器。 字线驱动器耦合到第一，第二和第三电源电压源，并且响应于识别第一，第二和第三电源电压源的地址信号，用来自第一电源电压源或第二电源电压源的字线电压选择性地驱动字线组中的字线 各自的司机。 第二电源电压源包括一组电源电压选择器。 该组中的每个电源电压选择器与该组驱动器的子集耦合。 驱动器的子集与阵列中的相应段耦合。 电源电压选择器响应于识别相应段的地址信号，在擦除模式期间选择负擦除电源电压或擦除禁止电源电压。 所选择的否定擦除电源电压或擦除禁止电源电压被施加到该组驱动器的子集，该组被分段地连接到相应的段。

公开(公告)号：US20110012658A1

公开(公告)日：2011-01-20

申请号：US12458570

申请日：2009-07-16

申请人： Shun-An Hsieh ,  Yu-Shen Lin

发明人： Shun-An Hsieh ,  Yu-Shen Lin

IPC分类号： H03K7/08

CPC分类号： H03K7/08

摘要： An adaptive pulse width control power conversion device includes a pulse width adjustable pulse frequency module (PFM) control circuit, a pulse width modulation (PWM) control circuit, a PWM/PFM switching unit, a switching circuit, and a load status detection circuit. When the power conversion device is to be switched from a PWM mode to a PFM mode, pulse width of a series of PFM control signals is sequentially adjusted from a low value to a high value according to a predetermined pulse width increment until an optimum pulse width is determined and thereafter, an output voltage is supplied to a load in the PFM mode, whereby ripple of output voltage in the PFM mode can be improved and improved stability of output of the power conversion device is realized.

摘要翻译： 一种自适应脉宽控制电源转换装置，包括脉冲宽度可调脉冲频率模块（PFM）控制电路，脉宽调制（PWM）控制电路，PWM / PFM切换单元，开关电路和负载状态检测电路。 当将功率转换装置从PWM模式切换到PFM模式时，一系列PFM控制信号的脉冲宽度根据预定的脉冲宽度增量从低值依次调整为高值，直到最佳脉冲宽度 然后在PFM模式中向负载提供输出电压，从而可以提高PFM模式中的输出电压的波动，并且实现电力转换装置的输出的稳定性的提高。

公开(公告)号：US07227764B2

公开(公告)日：2007-06-05

申请号：US11286204

申请日：2005-11-23

申请人： Lung-Yi Chueh ,  Yu-Shen Lin

发明人： Lung-Yi Chueh ,  Yu-Shen Lin

IPC分类号： H02M3/18 ,  H02M3/02

CPC分类号： H02M3/073 ,  H02M1/143 ,  H02M1/15 ,  H02M2003/075

摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.

摘要翻译： 公开了一种用于电荷泵的电压调节装置。 电荷泵根据至少一个时钟信号的工作输出输出电压。 电压调节装置至少包括一个电压调节电容器和至少一个逆变器。 逆变器用于接收时钟信号并相应地输出反相时钟信号。 电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。

公开(公告)号：US07082061B2

公开(公告)日：2006-07-25

申请号：US11003092

申请日：2004-12-03

申请人： Sheree Chou ,  Lung-Yi Chueh ,  Yu-Shen Lin

发明人： Sheree Chou ,  Lung-Yi Chueh ,  Yu-Shen Lin

IPC分类号： G11C7/00 ,  G11C16/06

CPC分类号： G11C7/12 ,  G11C16/24

摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.

摘要翻译： 提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。 夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。 比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。 比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线 具有接近目标水平的电压。

公开(公告)号：US06975549B1

公开(公告)日：2005-12-13

申请号：US10863924

申请日：2004-06-08

申请人： Yu-Shen Lin

发明人： Yu-Shen Lin

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/14 ,  G11C16/28 ,  G11C2207/063 ,  G11C2207/2227

摘要： Low power sense amplifier for amplifying a small current difference associated with a memory cell of a memory array is disclosed. The sense amplifier is connected with a memory array having multiple of even columns and multiple of odd columns. A small read current representing the digital data stored at a memory cell is obtained from the memory array via one of the two complementary data lines. The sense amplifier builds a small voltage difference based on a difference between the small read current and a small reference current obtained from a memory array, and amplifies the small voltage difference to produce two amplified signals. One of the amplified signals is selected by the sense amplifier using an even/odd column decoding scheme. The memory array also uses the even/odd column decoding scheme to output the read current to one of the two complementary data lines. A method for how to use the disclosed sense amplifier is also described.

摘要翻译： 公开了用于放大与存储器阵列的存储器单元相关联的小电流差的低功率读出放大器。 读出放大器与具有多个偶数列和奇数列的多个的存储器阵列连接。 代表存储在存储单元中的数字数据的小的读取电流通过两条补充数据线之一从存储器阵列获得。 读出放大器基于小的读取电流和从存储器阵列获得的小的参考电流之间的差异构建小的电压差，并且放大小的电压差以产生两个放大的信号。 其中一个放大信号由读/放置器使用偶/奇列解码方案选择。 存储器阵列还使用偶/奇列解码方案将读取电流输出到两条互补数据线之一。 还描述了如何使用所公开的读出放大器的方法。