公开(公告)号：US06303453B1

公开(公告)日：2001-10-16

申请号：US09329030

申请日：1999-06-09

申请人： Jurriaan Schmitz ,  Pierre H. Woerlee

发明人： Jurriaan Schmitz ,  Pierre H. Woerlee

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2255 ,  H01L21/31155

摘要： The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (IA) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.

摘要翻译： 本发明涉及制造（水平）MOST的方法，例如在（BI）CMOS IC中使用的MOST。 在栅电极（2）的任一侧上，位于栅极氧化物（IA）上方的硅衬底（10,11）的表面在源（3）的位置处设置有电介质层（1B） 并形成漏极（4），该介质层包括形成为起始层的热氧化物层（1B）。 源极（3）和/或漏极（4）设置有LDD区域（3A，4A），源极（3）和漏极（4）的其余部分（3B，4B）由离子注入 （I1）掺杂到硅衬底（10,11）中。 以这种方式获得的MOST仍然遭受所谓的短沟道效应，导致阈值电压对栅电极（2）的长度的实质依赖性，特别是在非常短的栅电极长度的情况下 （2）。 在根据本发明的方法中，LDD区域（3A，4A）如下制造：在第一步骤中，在第二离子注入（I2）中，将合适的掺杂原子（D）注入介电层（1B） ，随后在第二步骤中，掺杂原子（D）的一部分从电介质层（1B）扩散到硅衬底（10,11）中，由此形成LDD区域（3A，4A）。 该方法使得能够获得具有优异性能的MOST，例如与常规制作的MOST（曲线131）相比，阈值电压相对于栅电极（2）长度（曲线130）的平坦轮廓。 该结果以简单且可再现的方式获得。

公开(公告)号：US5966616A

公开(公告)日：1999-10-12

申请号：US44499

申请日：1998-03-19

申请人： Pierre H. Woerlee

发明人： Pierre H. Woerlee

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/316 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A method of manufacturing a semiconductor device, in which trenches (7) are formed in a surface (2) of a silicon body (1), which trenches are filled with silicon oxide (11). The filled trenches are used as field-oxide regions (12) in integrated circuits. The silicon oxide is deposited from a gas phase and is subsequently densified by means of a thermal treatment in an NO or N.sub.2 O-containing atmosphere. The deposited silicon oxide can be densified in a very short period of time, and, in addition, the thermal treatment does not cause crystal defects. The method can suitably be used for "single wafer processing".

摘要翻译： 一种半导体器件的制造方法，其中沟槽（7）形成在硅体（1）的表面（2）中，所述沟槽填充有氧化硅（11）。 填充的沟槽用作集成电路中的场氧化物区域（12）。 氧化硅由气相沉积，随后通过在含NO或N 2 O的气氛中的热处理而致密化。 沉积的氧化硅可以在非常短的时间内致密化，另外，热处理不会引起晶体缺陷。 该方法可以适用于“单晶片处理”。

公开(公告)号：US06403426B1

公开(公告)日：2002-06-11

申请号：US09527202

申请日：2000-03-16

申请人： Andreas H. Montree ,  Jurriaan Schmitz ,  Pierre H. Woerlee

发明人： Andreas H. Montree ,  Jurriaan Schmitz ,  Pierre H. Woerlee

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： In a method of manufacturing a semiconductor device comprising a transistor having a gate insulated from a channel region at a surface of a semiconductor body by a gate dielectric, an active region 4 of a first conductivity type is defined at the surface 2 of the semiconductor body 1, and a patterned layer is applied consisting of refractory material, which patterned layer defines the area of the planned gate to be provided at a later stage of the process and acts as a mask during the formation of a source zone 11 and a drain zone 12 of a second conductivity type in the semiconductor body 1. In a next step, a dielectric layer 14 is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer 14 is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess 15 in the dielectric layer 14 at the area of the planned gate. Then, impurities are introduced via the recess 15 into the channel region 13 of the semiconductor body 1 in a self-registered way by using the dielectric layer 14, as a mask and an insulating layer is applied, forming the gate dielectric, on which insulating layer a conductive layer is applied thereby filling the recess, which conductive layer is shaped into the gate of the transistor.

摘要翻译： 在制造半导体器件的方法中，该半导体器件包括晶体管，该晶体管具有通过栅极电介质在半导体本体的表面处与沟道区绝缘的栅极，在半导体本体的表面2处限定第一导电类型的有源区域4 1，并且施加由耐火材料组成的图案层，该图案层限定了将在该工艺的稍后阶段提供的规划浇口的区域，并且在形成源区11和排水区期间用作掩模 在下一步骤中，提供电介质层14，其厚度足够大以覆盖图案化层，该电介质层14通过部分厚度被去除其厚度的一部分，借助于 直到图案化层被暴露之前的材料去除处理，去除图案层，从而在计划的栅极的区域处在电介质层14中形成凹陷15。 然后，通过使用电介质层14作为掩模，并且施加绝缘层，通过凹部15将杂质以自我注册的方式引入半导体本体1的沟道区域13中，形成栅极电介质，绝缘 施加导电层，从而填充凹部，该导电层被成形为晶体管的栅极。

公开(公告)号：US06251729B1

公开(公告)日：2001-06-26

申请号：US09464004

申请日：1999-12-15

申请人： Andreas H. Montree ,  Jurriaan Schmitz ,  Pierre H. Woerlee

发明人： Andreas H. Montree ,  Jurriaan Schmitz ,  Pierre H. Woerlee

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11539 ,  H01L29/66545

摘要： In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type. In a next step, a dielectric layer is applied, which is removed over at least part of its thickness by means of a material removing treatment until the silicon-containing layer at the first and the second active region and is exposed, after which the silicon-containing first active region are removed, thereby forming a recess in the dielectric layer. Subsequently, a second insulating layer is applied at the second active region providing an inter-gate dielectric of the memory element, and a third insulating layer is applied at the first active region providing a gate dielectric of the transistor. After formation of the gate dielectric and the inter-gate dielectric, a conductive layer is applied which is shaped into a gate of the transistor at the first active region and a control gate of the memory element at the second active region.

摘要翻译： 在半导体本体的表面上制造包括场效晶体管和非易失性存储元件的半导体器件的方法中，第一导电类型的第一和第二有源区限定在半导体本体的表面 分别用于晶体管和存储器元件。 半导体本体的表面随后涂覆有提供晶体管的牺牲栅极电介质和存储元件的浮置栅极电介质的第一绝缘层，该第一绝缘层然后被含硅层覆盖，所述含硅层提供牺牲栅极 晶体管和存储元件的浮动栅极。 在形成牺牲栅极和浮置栅极之后，晶体管和存储元件设置有第二导电类型的源区和漏区。 在下一步骤中，施加电介质层，其通过材料去除处理至少部分其厚度去除，直到在第一和第二有源区域处的含硅层被暴露，然后将硅 除去第一有源区，从而在电介质层中形成凹部。 随后，在第二有源区施加第二绝缘层，提供存储元件的栅极间电介质，并且在提供晶体管的栅极电介质的第一有源区施加第三绝缘层。 在形成栅极电介质和栅极间电介质之后，施加导电层，该导电层在第一有源区域被成形为晶体管的栅极，并且在第二有源区域处形成存储元件的控制栅极。

公开(公告)号：US06177303B1

公开(公告)日：2001-01-23

申请号：US09379959

申请日：1999-08-24

申请人： Jurriaan Schmitz ,  Pierre H. Woerlee ,  Andreas H. Montree

发明人： Jurriaan Schmitz ,  Pierre H. Woerlee ,  Andreas H. Montree

IPC分类号： H01L21337

CPC分类号： H01L29/6659 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545

摘要： In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).

摘要翻译： 在已知的替代栅极工艺中，通过沉积厚的氧化物层，然后通过CMP平坦化该层，直到达到栅极，该相对高欧姆的多晶硅栅极被低欧姆金属栅极代替，该栅极可被选择性地去除和替换 由金属门。 通过将栅极结构设置为多晶硅栅极顶部的虚设多晶硅栅极（4）和氮化物层（5）的叠层，可大大简化工艺。 当在CMP期间达到氮化物层时，停止CMP，从而排除对聚合物的攻击。 相对于氧化物层（10）选择性地去除氮化物和多晶硅。

公开(公告)号：US5550773A

公开(公告)日：1996-08-27

申请号：US380536

申请日：1995-01-30

申请人： Pierre H. Woerlee ,  Cornelis M. Hart

发明人： Pierre H. Woerlee ,  Cornelis M. Hart

IPC分类号： H01L21/8247 ,  H01L23/525 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/105 ,  H01L23/5252 ,  H01L2924/0002

摘要： The invention relates to a semiconductor memory with a semiconductor body which is provided at a surface with a system of memory elements arranged in rows and columns. For addressing, the surface is provided with a system of mutually adjacent parallel selection lines 4, each coupled at one end to a selection transistor 19 with which the connection between the selection line and peripheral electronics can be opened or closed. These transistors are thin-film transistors which are formed, for example, in the selection lines themselves. As a result of this, the selection lines, and thus also the memory elements in the matrix, can be provided with minimum pitch.

摘要翻译： 本发明涉及具有半导体本体的半导体存储器，该半导体本体在表面设置有以行和列排列的存储元件系统。 为了寻址，表面设置有相互相邻的并行选择线4的系统，每个系统在一端耦合到选择晶体管19，选择线和外围电子器件之间的连接可以被打开或关闭。 这些晶体管是例如在选择线本身中形成的薄膜晶体管。 结果，选择线以及矩阵中的存储元件也可以以最小间距提供。

公开(公告)号：US06291352B1

公开(公告)日：2001-09-18

申请号：US09167819

申请日：1998-10-07

申请人： Pierre H. Woerlee ,  Casparus A. H. Juffermans ,  Andreas H. Montree

发明人： Pierre H. Woerlee ,  Casparus A. H. Juffermans ,  Andreas H. Montree

IPC分类号： H01L21311

CPC分类号： H01L23/5252 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76813 ,  H01L2924/0002 ,  Y10S438/933 ,  H01L2924/00

摘要： Amorphous or polycrystalline silicon layers are sometimes used in the metallization steps of IC processes, for example as antireflex coatings or as etching stopper layers for etching back of tungsten. A problem is that such a layer cannot be provided by CVD or LPCVD on account of the high deposition temperature which is not compatible with standard Al metallizations. Other deposition techniques, such as sputtering or plasma CVD, often lead to a lesser material quality, a longer processing time per wafer, or a worse step covering. According to the invention, the layer is provided by CVD or LPCVD at a temperature below 500° C. under the addition of Ge. The GexSi1−x layer (8) thus obtained is found to have good properties as regards step covering, optical aspects, electrical aspects, and etching aspects, and is compatible with any Al metallization (6) already present.

摘要翻译： 有时在IC工艺的金属化步骤中使用无定形或多晶硅层，例如作为抗反射涂层或用于蚀刻钨的蚀刻停止层。 一个问题是，由于与标准Al金属化不兼容的高沉积温度，这种层不能通过CVD或LPCVD提供。 诸如溅射或等离子体CVD的其它沉积技术通常导致较小的材料质量，每个晶片的更长的处理时间或较差的步骤覆盖。 根据本发明，通过CVD或LPCVD在低于500℃的温度下，在Ge的添加下提供该层。 发现如此获得的GexSi1-x层（8）在步骤覆盖，光学方面，电学方面和蚀刻方面具有良好的性能，并且与已经存在的任何Al金属化（6）兼容。

公开(公告)号：US06271551B1

公开(公告)日：2001-08-07

申请号：US08764914

申请日：1996-12-13

申请人： Jurriaan Schmitz ,  Pierre H. Woerlee

发明人： Jurriaan Schmitz ,  Pierre H. Woerlee

IPC分类号： H01L2976

CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083

摘要： To obtain a high mobility and a suitable threshold voltage in MOS transistors with channel dimensions in the deep sub-micron range, it is desirable to bury a strongly doped layer (or ground plane) in the channel region below a weakly doped intrinsic surface region, a few tens of nm below the surface. It was found, however, that degradation of the mobility can occur particularly in n-channel transistors owing to diffusion of boron atoms from the strongly doped layer to the surface, for example during the formation of the gate oxide. To prevent this degradation, a thin layer 11 of Si1−xGex inhibiting boron diffusion is provided between the strongly doped layer 10 and the intrinsic surface region 7, for example with x=0.3. The SiGe layer and the intrinsic surface region may be provided epitaxially, the thickness of the SiGe layer being so small that the lattice constants in the epitaxial layers do not or substantially not differ from those in the substrate 1 in a plane parallel to the surface, while a sufficient diffusion-inhibiting effect is retained. Since SiGe has a diffusion-accelerating rather than decelerating effect on n-type dopants, the ground plane of a p-channel transistor in a CMOS embodiment is doped with As or Sb because of the low diffusion rate of these elements in pure silicon.

摘要翻译： 为了在具有深亚微米范围的沟道尺寸的MOS晶体管中获得高迁移率和合适的阈值电压，期望在弱掺杂的本征表面区域下面的沟道区域中埋设强掺杂层（或接地平面） 在表面下方几十nm。 然而，已经发现，由于硼原子从强掺杂层扩散到表面，例如在形成栅极氧化物期间，特别是在n沟道晶体管中可能发生迁移率的降低。 为了防止这种劣化，例如在x = 0.3处，在强掺杂层10和固有表面区域7之间设置抑制硼扩散的Si1-xGex薄层11。 可以外延地提供SiGe层和本征表面区域，SiGe层的厚度如此之小，使得外延层中的晶格常数与平行于表面的平面中的衬底1中的晶格常数没有或基本上没有不同， 同时保留足够的扩散抑制作用。 由于SiGe对n型掺杂剂具有扩散加速而不是减速效应，所以CMOS实施例中的p沟道晶体管的接地面由于在纯硅中这些元素的低扩散速率掺杂有As或Sb。

公开(公告)号：US5416343A

公开(公告)日：1995-05-16

申请号：US306854

申请日：1994-09-15

申请人： Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

发明人： Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L27/10 ,  G11C17/00 ,  H01L27/04

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/91

摘要： A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.PROG can be applied between the column and row conductors associated with the element to be programmed during operation, which voltage is greater than the breakdown voltage of at least a portion of the insulating layer (8) situated between the semiconductor region (10) and the conductor region (20) of the element. The programming voltage is applied with such a polarity that majority charge carriers in the semiconductor region (10) are drawn to an interface (4) between the semiconductor region (10) and the insulating layer (8), forming an accumulation layer (31) there. Between the remaining column and row conductors, on the other hand, the programming voltage is offered with an opposite polarity. Thus the programming of the matrix can take place, if so desired, by means of only a single voltage level V.sub.PROG.

摘要翻译： 半导体器件包括以行和列的矩阵排列的多个可编程元件。 这些元件各自具有由绝缘层（8）相互分离的掺杂半导体区域（10）和导体区域（20）。 导体区域（20）可以是适于与半导体区域（10）的材料形成整流结（35）的材料。 在一行内，其中存在的可编程元件的导体区域耦合到公共行导体（21 ... 23），并且在列内，位于其中的可编程元件的半导体区域连接到公共列导体（11 ... 14）。 为了对元件进行编程，编程电压VPROG可以施加在与要在操作期间被编程的元件相关联的列和行导体之间，该电压大于位于第二绝缘层（8）的至少一部分的击穿电压 半导体区域（10）和元件的导体区域（20）。 施加编程电压，使得半导体区域（10）中的多数电荷载流子被吸引到半导体区域（10）和绝缘层（8）之间的界面（4）上，形成蓄积层（31） 那里。 另一方面，在剩余的列和导体之间，以相反的极性提供编程电压。 因此，如果需要，可以仅通过单个电压电平VPROG来进行矩阵的编程。