公开(公告)号：US20100031067A1

公开(公告)日：2010-02-04

申请号：US12183099

申请日：2008-07-31

申请人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

IPC分类号： G06F1/03

CPC分类号： G06F1/03 ,  G06F1/26

摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。

公开(公告)号：US20090254781A1

公开(公告)日：2009-10-08

申请号：US12479914

申请日：2009-06-08

申请人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

发明人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

IPC分类号： G06F11/07

CPC分类号： G06F1/04

摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

公开(公告)号：US20090109781A1

公开(公告)日：2009-04-30

申请号：US11924935

申请日：2007-10-26

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F2212/1056 ,  G11C7/1006

摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电荷存储装置，其耦合到数据保持装置，使得数据保持装置的使用触发电荷源对电荷存储装置的充电; 以及用于测量电荷存储装置的电位的装置，所述测量装置通信地耦合到基于所测量的电位确定数据保持装置的相对使用量的计算平均值。

公开(公告)号：US20090031111A1

公开(公告)日：2009-01-29

申请号：US11828705

申请日：2007-07-26

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3897 ,  G06F15/7867

摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。

公开(公告)号：US20090024972A1

公开(公告)日：2009-01-22

申请号：US12163025

申请日：2008-06-27

申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

公开(公告)号：US20090024859A1

公开(公告)日：2009-01-22

申请号：US11870575

申请日：2007-10-11

申请人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

发明人： Kenneth J GOODNOW ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

IPC分类号： G06F1/32

CPC分类号： G06F1/26

摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

公开(公告)号：US20090021085A1

公开(公告)日：2009-01-22

申请号：US11866537

申请日：2007-10-03

申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, JR. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, JR. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： H01H37/32

CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

公开(公告)号：US20080320286A1

公开(公告)日：2008-12-25

申请号：US12197613

申请日：2008-08-25

申请人： John E. Campbell ,  William T. Devine ,  Sebastian T. Ventrone

发明人： John E. Campbell ,  William T. Devine ,  Sebastian T. Ventrone

IPC分类号： G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/3017

摘要： A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.

摘要翻译： 一种用于提高计算机处理器中的对象级指令流的效率的系统和方法。 用于在RISC架构的计算机处理器中从对象级指令流生成翻译指令的翻译逻辑和执行翻译指令的执行单元集成到处理器中。 翻译逻辑将多个对象级指令的功能组合成单个转换的指令，该指令与非翻译指令相比可以被分派到单个执行单元，否则将被顺序地分派到单独的执行单元。 因此，可以扩展处理器的吞吐量，因为每个周期可以调度的指令的数量被扩展。

公开(公告)号：US20080290896A1

公开(公告)日：2008-11-27

申请号：US12185467

申请日：2008-08-04

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 可重构逻辑阵列（RLA）系统，其包括RLA和用于在循环基础上重新编程RLA的编程器。 需要比RLA中包含的逻辑量​​大的函数（F）被划分为多个功能块。 程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：US20080229265A1

公开(公告)日：2008-09-18

申请号：US12129748

申请日：2008-05-30

申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F1/10 ,  G06F17/5045

摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

摘要翻译： 公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。 特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。