公开(公告)号：US5930826A

公开(公告)日：1999-07-27

申请号：US833599

申请日：1997-04-07

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G06F12/14 ,  G11C16/22

CPC分类号： G06F12/1425 ,  G11C16/22

摘要： Flash memory circuits provide sector protection or file protection with protection attribute status bits held in a flash memory array. The sector protection protects memory data based on the physical location of the data. The flash memory array is divided into a number of memory sectors. Each memory sector can be protected independently. The size of the memory sector is flexible and may be as large as the whole memory array or as small as a single bit group. Each memory sector has protection bits stored in a protection bit array for indicating the protection state of the sector. A parallel protection structure providing both sector protection and block protection is also included. The parallel protection allows small size data protection as well as large size block protection. File protection protects memory data on a file basis regardless of the physical location of the data. Each file has protection bits stored in an attribute memory for indicating the protection state of the file. The attribute memory is made from part of the flash memory which simplifies the process of manufacturing the memory. It also reduces the area size of the attribute memory and the complexity of the control circuits.

摘要翻译： 闪存电路提供扇区保护或文件保护，保护属性状态位保存在闪存阵列中。 扇区保护基于数据的物理位置来保护存储器数据。 闪存阵列被分成多个存储器扇区。 每个内存扇区都可以独立保护。 存储器扇区的大小是灵活的，并且可以与整个存储器阵列一样大，或者与单个位组一样小。 每个存储器扇区具有存储在保护位阵列中的保护位，用于指示扇区的保护状态。 还包括提供扇区保护和块保护的并行保护结构。 并行保护允许小尺寸数据保护以及大尺寸块保护。 文件保护以文件为基础保护存储器数据，而不管数据的物理位置如何。 每个文件具有存储在属性存储器中的保护位，用于指示文件的保护状态。 属性存储器由闪存的一部分制成，这简化了存储器的制造过程。 它还减少了属性存储器的面积大小和控制电路的复杂性。

公开(公告)号：US09063849B2

公开(公告)日：2015-06-23

申请号：US13200141

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G06F12/00 ,  H05K3/00 ,  G06F12/06 ,  G06F12/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/00 ,  G11C16/32

CPC分类号： G06F12/0638 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C11/005 ,  G11C16/32 ,  G11C2216/30 ,  Y02D10/13 ,  Y10T29/49124

摘要： A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

摘要翻译： 半导体芯片在一个存储器芯片中包含四种不同的存储器类型，EEPROM，NAND闪存，NOR闪存和SRAM以及多个主要的串行/并行接口，例如I2C，SPI，SDI和SQI。 内存芯片具有写时同时写入和读写操作以及读写同时传输和写时同时传输操作。 存储器芯片提供八个引脚，其中两个用于供电，最多四个引脚没有连接用于特定接口，并且使用新颖的统一的非易失性存储器设计，允许集成在一起的上述存储器类型集成在同一半导体存储器芯片 。

公开(公告)号：US08773903B2

公开(公告)日：2014-07-08

申请号：US13535681

申请日：2012-06-28

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0425 ,  H01L27/11519 ,  H01L27/11521

摘要： A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

摘要翻译： 双晶体管NOR闪存单元具有由基于NAND的制造工艺制造的对称的源极和漏极结构。 闪存单元包括由双多晶硅NMOS浮栅晶体管构成的存储晶体管和由双多晶硅NMOS浮栅晶体管构成的存取晶体管，poly1和poly2短路的poly1NMOS晶体管或单聚poly1或poly2 NMOS晶体管。 使用Fowler-Nordheim通道隧道方案对闪存单元进行编程和擦除。 基于NAND的闪速存储器件包括与并行位线排列的闪存单元的阵列和垂直于字线的源极线。 写行解码器和读行解码器专为闪存器件而设计，可在预编程中为闪速存储器阵列提供适当的电压，通过验证，擦除，以页面，块为单位进行验证，编程和读取操作， 部门或芯片。

公开(公告)号：US08335108B2

公开(公告)日：2012-12-18

申请号：US12291913

申请日：2008-11-14

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L29/7923

摘要： A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line.

摘要翻译： 连接到双极电荷捕获非易失性存储器单元的组的NAND系列的顶部和可选地连接到底部的具有串联连接的阈值电压可调选择晶体管的非易失性存储器结构，用于控制NAND系列串与 关联位线。 阈值电压可调选择晶体管中的第一个阈值电压电平被调整到第一阈值电压电平，而阈值电压可调选择晶体管中的第二阈值电压调整到第二阈值电压电平。 一对串联连接的阈值电压可调选择晶体管连接到两个相关位线中的第一个。 NAND非易失性存储器串还连接到连接到第二关联位线的一对串联连接的阈值电压可调底部选择晶体管。

公开(公告)号：US08295087B2

公开(公告)日：2012-10-23

申请号：US12456354

申请日：2009-06-16

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C16/04 ,  G11C11/4193

CPC分类号： G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459

摘要： A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.

摘要翻译： 非易失性存储器件包括EEPROM配置的非易失性存储单元的阵列，每个存储单元具有用于存储数字数据的浮动栅极存储晶体管和用于激活用于读取，编程和擦除的浮动栅极存储晶体管的浮动栅极选择晶体管。 非易失性存储器件具有行解码器，用于将操作偏置电压电平传送到连接到浮置栅极存储晶体管的字线，用于读取，编程，验证和擦除所选择的非易失性存储器单元。 非易失性存储器件具有选择栅极解码器电路，将选择栅极控制偏置电压传输到连接到浮置栅极选择晶体管的控制栅极的选择栅极控制线，用于读取，编程，验证和擦除所选择的浮置栅极存储晶体管 非易失性存储单元。 产生操作偏置电压电平以最小化操作干扰并防止外围设备中的漏极损耗。

公开(公告)号：US08233320B2

公开(公告)日：2012-07-31

申请号：US12829391

申请日：2010-07-02

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0425 ,  H01L27/11519 ,  H01L27/11521

摘要： A two transistor NOR flash memory cell has symmetrical source and drain structure manufactured by a NAND-based manufacturing process. The flash cell comprises a storage transistor made of a double-poly NMOS floating gate transistor and an access transistor made of a double-poly NMOS floating gate transistor, a poly1 NMOS transistor with poly1 and poly2 being shorted or a single-poly poly1 or poly2 NMOS transistor. The flash cell is programmed and erased by using a Fowler-Nordheim channel tunneling scheme. A NAND-based flash memory device includes an array of the flash cells arranged with parallel bit lines and source lines that are perpendicular to word lines. Write-row-decoder and read-row-decoder are designed for the flash memory device to provide appropriate voltages for the flash memory array in pre-program with verify, erase with verify, program and read operations in the unit of page, block, sector or chip.

摘要翻译： 双晶体管NOR闪存单元具有由基于NAND的制造工艺制造的对称的源极和漏极结构。 闪存单元包括由双多晶硅NMOS浮栅晶体管构成的存储晶体管和由双多晶硅NMOS浮栅晶体管构成的存取晶体管，poly1和poly2短路的poly1NMOS晶体管或单聚poly1或poly2 NMOS晶体管。 使用Fowler-Nordheim通道隧道方案对闪存单元进行编程和擦除。 基于NAND的闪速存储器件包括与并行位线排列的闪存单元的阵列和垂直于字线的源极线。 写行解码器和读行解码器专为闪存器件而设计，可在预编程中为闪速存储器阵列提供适当的电压，通过验证，擦除，以页面，块为单位进行验证，编程和读取操作， 部门或芯片。

公开(公告)号：US20120176841A1

公开(公告)日：2012-07-12

申请号：US13347913

申请日：2012-01-11

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0441 ,  G11C16/10

摘要： A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0.

摘要翻译： 公开了一种用于PLD，PAL和匹配功能的NAND阵列的基于NVM的2T或2nT NAND单元。 优选的NVM单元可以是ROM或Flash。 2T闪存单元优选地使用FN进行编程和擦除操作，而2T ROM单元优选地将磷用于ROM代码注入来获得负Vt0。

公开(公告)号：US20120069651A1

公开(公告)日：2012-03-22

申请号：US13200142

申请日：2011-09-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/10 ,  G11C16/06 ,  H01L21/336 ,  H01L29/788

CPC分类号： G11C16/0416 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/7883

摘要： A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

摘要翻译： 非易失性存储器件具有FLOTOX EEPROM非易失性存储器阵列的组合。 每个基于FLOTOX的非易失性存储器阵列由基于FLOTOX的非易失性存储器单元形成，其包括至少一个浮置栅极隧穿氧化物晶体管，使得控制栅极与浮置栅极隧道氧化物晶体管的浮置栅极的耦合比率约为60 ％至约70％，并且将浮置栅极与漏极区域的浮动栅极氧化物晶体管的耦合比保持为约10％至约20％的常数，并且使得沟道区的沟道长度为 减小，使得在编程过程期间将负编程电压电平施加到控制栅极，并且向漏极区域施加中等的正编程电压电平，以防止中等正编程电压电平超过漏源至源极击穿电压。

公开(公告)号：US08120959B2

公开(公告)日：2012-02-21

申请号：US12455337

申请日：2009-06-01

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3436 ,  G11C2211/5644

摘要： A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines.

摘要翻译： 非易失性存储器件包括非易失性存储器阵列，其包括以行和列排列的多个电荷保持晶体管。 该装置具有与与每列相关联的位线并联形成的多条源极线。 行解码/驱动器电路连接到电荷保持晶体管的块，用于控制所需的读取，编程和擦除信号的应用。 擦除计数寄存器，每个擦除计数寄存器与电荷保持晶体管阵列的一个块相关联，用于存储相关块的擦除计数，以确定是否执行刷新操作。 电荷保持晶体管阵列的每列上的分组被连接为NAND串联串行，其中每个NAND串具有连接到顶部电荷保持晶体管的选择栅极电荷保持晶体管，用于将NAND串联连接到位线。

公开(公告)号：US20120001233A1

公开(公告)日：2012-01-05

申请号：US13135220

申请日：2011-06-29

申请人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Han-Rei Ma ,  Fu-Chang Hsu

IPC分类号： H01L23/52 ,  H01L21/8246

CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66825 ,  H01L29/7881

摘要： An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

摘要翻译： 由非易失性存储器阵列电路，逻辑电路和线性模拟电路形成的集成电路形成在基板上。 非易失性存储器阵列电路，逻辑电路和线性模拟电路由通过浅沟槽隔离形成的隔离区隔开。 非易失性存储器阵列电路形成为三重阱结构。 非易失性存储器阵列电路是由至少两个串联连接的浮栅晶体管形成的基于NAND的NOR存储器电路，使得浮栅晶体管中的至少一个用作选择栅极晶体管，以防止漏电流通过电荷保持晶体管， 电荷保持晶体管不被选择用于读取。 基于NAND的NOR存储器电路的每列与一个位线和一个源极线相关联并连接到一个位线和一个源极线。