公开(公告)号：US06551944B1

公开(公告)日：2003-04-22

申请号：US09544717

申请日：2000-04-06

Applicant: Piero Giorgio Fallica ,  Davide Giuseppe Patti ,  Cirino Rapisarda

Inventor： Piero Giorgio Fallica ,  Davide Giuseppe Patti ,  Cirino Rapisarda

IPC: H01L2100

CPC classification number: H01L21/76232 ,  H01L21/763

Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract translation: 一种方法，包括以下步骤：在半导体材料体中进行定向蚀刻以形成具有第一宽度的沟槽; 在沟槽下进行半导体材料体的各向同性蚀刻，以形成宽度大于沟槽的空腔; 用介电材料覆盖空腔的壁; 沉积与热氧化物不同的非导电材料以至少部分地填充空腔，以形成与半导体材料体的其余部分分离的单晶岛。 各向同性蚀刻允许形成由半导体材料的支撑区域隔开的至少两个相邻的空腔，其与腔的壁一起被氧化，以在填充非导电材料之前提供对岛的支撑。

公开(公告)号：US08975607B2

公开(公告)日：2015-03-10

申请号：US13431831

申请日：2012-03-27

Applicant: Lucio Renna ,  Clelia Galati ,  Piero Giorgio Fallica

Inventor： Lucio Renna ,  Clelia Galati ,  Piero Giorgio Fallica

IPC: G01N21/01 ,  G02B21/00 ,  G01J1/04 ,  G01J1/44 ,  G01J1/02 ,  G01N21/64

CPC classification number: G02B21/0032 ,  G01J1/0266 ,  G01J1/0411 ,  G01J1/0437 ,  G01J1/0488 ,  G01J1/44 ,  G01N21/6452

Abstract: A confocal optical detector including a light source generating a first optical beam along an axis; an optoelectronic sensor; an optical focusing device, which receives and focuses the first optical beam; and a hole, which receives the first optical beam and is arranged between the optoelectronic sensor and the optical focusing device. The optoelectronic sensor is arranged between the light source and the hole. In addition, the optoelectronic sensor and the optical focusing device are aligned along the axis.

Abstract translation: 一种共焦光学检测器，包括沿轴线产生第一光束的光源; 光电传感器; 光聚焦装置，其接收和聚焦第一光束; 以及孔，其接收第一光束并且布置在光电传感器和光聚焦装置之间。 光电传感器布置在光源和孔之间。 此外，光电传感器和光学聚焦装置沿轴线对准。

公开(公告)号：US08778721B2

公开(公告)日：2014-07-15

申请号：US12356445

申请日：2009-01-20

Applicant: Delfo Nunziato Sanfilippo ,  Piero Giorgio Fallica

Inventor： Delfo Nunziato Sanfilippo ,  Piero Giorgio Fallica

IPC: H01L31/0232

CPC classification number: H01L31/107 ,  H01L25/167 ,  H01L27/14629 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.

Abstract translation: Geiger型雪崩光电二极管阵列的一个实施例，其中每个光电二极管由半导体材料体形成，具有第一导电类型并且容纳阳极区，第二导电类型面向主体的顶表面，阴极 接触区域，其具有第一导电类型和比主体更高的掺杂水平，面向主体的底表面;绝缘区域，其延伸穿过主体并将活动区域与身体的其余部分隔离;活动区域容纳 阳极区域和阴极接触区域。 绝缘区域由多晶硅的第一反射镜区域，金属材料的第二反射镜区域和电介质材料的通道停止区域形成，围绕第一和第二反射镜区域。

公开(公告)号：US08471293B2

公开(公告)日：2013-06-25

申请号：US12356464

申请日：2009-01-20

Applicant: Delfo Nunziato Sanfilippo ,  Emilio Antonio Sciacca ,  Piero Giorgio Fallica ,  Salvatore Antonio Lombardo

Inventor： Delfo Nunziato Sanfilippo ,  Emilio Antonio Sciacca ,  Piero Giorgio Fallica ,  Salvatore Antonio Lombardo

IPC: H01L31/107

CPC classification number: H01L27/1446 ,  H01L27/14658 ,  H01L27/14689 ,  H01L31/107

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

公开(公告)号：US07898008B2

公开(公告)日：2011-03-01

申请号：US11779681

申请日：2007-07-18

Applicant: Piero Giorgio Fallica ,  Roberto Modica

Inventor： Piero Giorgio Fallica ,  Roberto Modica

IPC: H01L21/70

CPC classification number: H01L21/84 ,  H01L21/82285 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/7317 ,  H01L29/732

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract translation: 双极器件集成在有源层中，其中限定沟槽包围容纳互补类型的双极晶体管的相应有源区域。 每个活动区容纳埋层; 在掩埋层的顶部延伸的阱区; 在所述装置的表面和所述阱区之间延伸的顶部沉降片区域; 在阱区域的顶部延伸并且相对于顶部沉降片区域横向延伸的掩埋收集器区域; 基部区域，相对于顶部沉降片区域横向延伸在埋藏的收集器区域的顶部上; 以及在基极区域内延伸的发射极区域。 互补晶体管的同源区具有相似的掺杂水平，通过外延层的离子注入获得，其中在生长期间添加的掺杂剂的浓度非常低，可能为零。

公开(公告)号：US07847360B2

公开(公告)日：2010-12-07

申请号：US11810701

申请日：2007-06-05

Applicant: Giuseppina Valvo ,  Piero Giorgio Fallica ,  Stefano Agosteo ,  Alberto Fazzi

Inventor： Giuseppina Valvo ,  Piero Giorgio Fallica ,  Stefano Agosteo ,  Alberto Fazzi

IPC: H01L31/0352

CPC classification number: H01L31/103 ,  H01L27/1463 ,  H01L31/115

Abstract: A radiation detector of the ΔE-E type is proposed. The detector is integrated in a chip of semiconductor material with a front surface and a back surface opposite the front surface, the detector having at least one detection cell arranged on the front surface for receiving a radiation to be evaluated, wherein the detector includes: a first region of a first type of conductivity extending into the chip from the front surface to a first depth; a second region of a second type of conductivity extending into the chip from the back surface to a second depth so as to reach the first region; and for each detection cell a third region of the second type of conductivity extending into the first region from the front surface to a third depth lower than the first depth and the second depth, a thin sensitive volume for absorbing energy from the radiation being defined by a junction between the first region and each third region, and a thick sensitive volume for absorbing further energy from the radiation being defined by a further junction between the first region and the second region. For each detection cell the detector further includes insulation means arranged around the third region and extending from the front surface into the first region to an insulation depth comprised between the first depth and the third depth.

Abstract translation: 提出了一种E-E型辐射探测器。 检测器集成在具有与前表面相对的前表面和后表面的半导体材料芯片中，检测器具有布置在前表面上的至少一个检测单元，用于接收待评估的辐射，其中检测器包括： 从前表面延伸到第一深度的第一类导电性的第一区域; 从第二深度延伸到芯片中的第二类导电体的第二区域，以便到达第一区域; 并且对于每个检测单元，第二类型的电导率的第三区域从前表面延伸到比第一深度和第二深度低的第三深度的第一区域，用于吸收来自辐射的能量的薄敏感体积由 第一区域和每个第三区域之间的接合点，以及用于吸收来自辐射的进一步能量的厚度敏感体积，由第一区域和第二区域之间的另一接合限定。 对于每个检测单元，检测器还包括设置在第三区域周围并且从前表面延伸到第一区域到包括在第一深度和第三深度之间的绝缘深度的绝缘装置。

公开(公告)号：US20080121807A1

公开(公告)日：2008-05-29

申请号：US11810701

申请日：2007-06-05

Applicant: Giuseppina Valvo ,  Piero Giorgio Fallica ,  Stefano Agosteo ,  Alberto Fazzi

Inventor： Giuseppina Valvo ,  Piero Giorgio Fallica ,  Stefano Agosteo ,  Alberto Fazzi

IPC: G01T1/02

CPC classification number: H01L31/103 ,  H01L27/1463 ,  H01L31/115

Abstract: A radiation detector of the ΔE-E type is proposed. The detector is integrated in a chip of semiconductor material with a front surface and a back surface opposite the front surface, the detector having at least one detection cell arranged on the front surface for receiving a radiation to be evaluated, wherein the detector includes: a first region of a first type of conductivity extending into the chip from the front surface to a first depth; a second region of a second type of conductivity extending into the chip from the back surface to a second depth so as to reach the first region; and for each detection cell a third region of the second type of conductivity extending into the first region from the front surface to a third depth lower than the first depth and the second depth, a thin sensitive volume for absorbing energy from the radiation being defined by a junction between the first region and each third region, and a thick sensitive volume for absorbing further energy from the radiation being defined by a further junction between the first region and the second region. For each detection cell the detector further includes insulation means arranged around the third region and extending from the front surface into the first region to an insulation depth comprised between the first depth and the third depth.

Abstract translation: 提出了DeltaE-E型辐射探测器。 检测器集成在具有与前表面相对的前表面和后表面的半导体材料芯片中，检测器具有布置在前表面上的至少一个检测单元，用于接收待评估的辐射，其中检测器包括： 从前表面延伸到第一深度的第一类导电性的第一区域; 从第二深度延伸到芯片中的第二类导电体的第二区域，以便到达第一区域; 并且对于每个检测单元，第二类型的电导率的第三区域从前表面延伸到比第一深度和第二深度低的第三深度的第一区域，用于吸收来自辐射的能量的薄敏感体积由 第一区域和每个第三区域之间的接合点，以及用于吸收来自辐射的进一步能量的厚度敏感体积，由第一区域和第二区域之间的另一接合限定。 对于每个检测单元，检测器还包括设置在第三区域周围并且从前表面延伸到第一区域到包括在第一深度和第三深度之间的绝缘深度的绝缘装置。

公开(公告)号：US20080017895A1

公开(公告)日：2008-01-24

申请号：US11779681

申请日：2007-07-18

Applicant: Piero Giorgio Fallica ,  Roberto Modica

Inventor： Piero Giorgio Fallica ,  Roberto Modica

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L21/82285 ,  H01L27/0826 ,  H01L27/1203 ,  H01L29/1004 ,  H01L29/66265 ,  H01L29/66272 ,  H01L29/7317 ,  H01L29/732

Abstract: A bipolar device is integrated in an active layer, wherein delimitation trenches surround respective active areas housing bipolar transistors of complementary types. Each active area accommodates a buried layer; a well region extending on top of the buried layer; a top sinker region extending between the surface of the device and the well region; a buried collector region extending on top of the well region and laterally with respect to the top sinker region; a base region, extending on top of the buried collector region laterally with respect to the top sinker region; and an emitter region extending inside the base region. The homologous regions of the complementary transistors have a similar doping level, being obtained by ion-implantation of epitaxial layers wherein the concentration of dopant added during the growth is very low, possibly zero.

Abstract translation: 双极器件集成在有源层中，其中限定沟槽包围容纳互补类型的双极晶体管的相应有源区域。 每个活动区容纳埋层; 在掩埋层的顶部延伸的阱区; 在所述装置的表面和所述阱区之间延伸的顶部沉降片区域; 在阱区域的顶部延伸并且相对于顶部沉降片区域横向延伸的掩埋收集器区域; 基部区域，相对于顶部沉降片区域横向延伸在埋藏的收集器区域的顶部上; 以及在基极区域内延伸的发射极区域。 互补晶体管的同源区具有相似的掺杂水平，通过外延层的离子注入获得，其中在生长期间添加的掺杂剂的浓度非常低，可能为零。

公开(公告)号：US06696741B1

公开(公告)日：2004-02-24

申请号：US09443742

申请日：1999-11-19

Applicant: Cesare Ronsisvalle ,  Piero Giorgio Fallica ,  Davide Patti

Inventor： Cesare Ronsisvalle ,  Piero Giorgio Fallica ,  Davide Patti

IPC: H01L2358

CPC classification number: H01L29/7802 ,  H01L21/762 ,  H01L29/0653

Abstract: PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.

Abstract translation: PN结结构，其包括第一导电类型的第一结区域和第二导电类型的第二结区域，其中在所述第一和第二接合区域之间提供掩埋绝缘材料区域格栅。