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114 条记录 (耗时 0.027 秒)

    Novel Metal/Polysilicon Gate Trench Power Mosfet
    11.
    发明申请
    Novel Metal/Polysilicon Gate Trench Power Mosfet 有权
    新型金属/多晶硅栅沟槽电源Mosfet

    公开(公告)号：US20140015037A1

    公开(公告)日：2014-01-16

    申请号：US13545131

    申请日：2012-07-10

    申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/283

    CPC分类号： H01L29/7813 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/0922 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7835

    摘要： The present disclosure relates to a power MOSFET device having a relatively low resistance hybrid gate electrode that enables good switching performance. In some embodiments, the power MOSFET device has a semiconductor body. An epitaxial layer is disposed on the semiconductor body. A hybrid gate electrode, which controls the flow of electrons between a source electrode and a drain electrode, is located within a trench extending into the epitaxial layer. The hybrid gate electrode has an inner region having a low resistance metal, an outer region having a polysilicon material, and a barrier region disposed between the inner region and the outer region. The low resistance of the inner region provides for a low resistance to the hybrid gate electrode that enables good switching performance for the power MOSFET device.

    摘要翻译： 本公开涉及具有相对低电阻的混合栅电极的功率MOSFET器件，其实现良好的开关性能。 在一些实施例中，功率MOSFET器件具有半导体本体。 外延层设置在半导体本体上。 控制源电极和漏电极之间的电子流的混合栅电极位于延伸到外延层中的沟槽内。 混合栅极具有具有低电阻金属的内部区域，具有多晶硅材料的外部区域和设置在内部区域和外部区域之间的阻挡区域。 内部区域的低电阻提供了对功率MOSFET器件具有良好开关性能的混合栅电极的低电阻。

    Trench power MOSFET
    17.
    发明授权
    Trench power MOSFET 有权
    沟槽功率MOSFET

    公开(公告)号：US08896060B2

    公开(公告)日：2014-11-25

    申请号：US13486681

    申请日：2012-06-01

    申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

    发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66734 ,  H01L21/02233 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66727 ,  H01L29/7813

    摘要： A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

    摘要翻译： 器件包括第一导电类型的半导体区域，延伸到半导体区域中的沟槽以及沟槽中的导电场板。 第一电介质层将场板的底部和侧壁与半导体区域分开。 主栅极设置在沟槽中并与场板重叠。 第二介电层设置在主栅极和场板之间并将其分离。 第一导电类型的掺杂漏极（DD）区域在第二介电层下面，其中主栅极的边缘部分与DD区域重叠。 身体区域包括与主门的一部分相同水平的第一部分和与DD区域相同水平并与其接触的第二部分，其中身体区域具有与第一导电性相反的第二导电类型 类型。

    FinFET with Trench Field Plate
    18.
    发明申请
    FinFET with Trench Field Plate 有权
    FinFET带沟槽场板

    公开(公告)号：US20140015048A1

    公开(公告)日：2014-01-16

    申请号：US13546738

    申请日：2012-07-11

    申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/401 ,  H01L29/0684 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66704 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7856

    摘要： An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

    摘要翻译： 一种集成电路器件包括：衬垫层，其具有主体部分，该主体部分具有横向邻近具有第二掺杂类型的漂移区域部分的第一掺杂型，形成在焊盘层中的沟槽，沟槽延伸穿过主体部分的界面和 漂移区部分，形成在沟槽中的栅极和沿着主体部分和漂移区部分的界面的焊盘层的顶表面上的栅极，形成在栅极的相对侧上的沟槽中的氧化物和嵌入的场板 在栅极的每个相对侧上的氧化物中。

    Apparatus and Method for Power MOS Transistor
    20.
    发明申请
    Apparatus and Method for Power MOS Transistor 有权
    功率MOS晶体管的装置和方法

    公开(公告)号：US20140015038A1

    公开(公告)日：2014-01-16

    申请号：US13546506

    申请日：2012-07-11

    申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7809 ,  H01L29/0649 ,  H01L29/10 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831

    摘要： A MOS transistor comprises a substrate, a first region formed over the substrate, a second region grown from the first region, a third region of formed in the second region, a first drain/source region formed in the third region, a first gate electrode formed in a first trench, a second drain/source region formed in the second region and on an opposite side of the first trench from the first drain/source region and a second trench coupled between the second drain/source region and the second region, wherein the second trench is of a same depth as the first trench.

    摘要翻译： MOS晶体管包括衬底，形成在衬底上的第一区域，从第一区域生长的第二区域，在第二区域中形成的第三区域，形成在第三区域中的第一漏极/源极区域，第一栅极电极 形成在第一沟槽中，第二漏极/源极区域形成在第二区域中，并且在第一沟槽与第一漏极/源极区域相反的一侧上，以及第二沟槽，其耦合在第二漏极/源极区域与第二区域之间， 其中所述第二沟槽具有与所述第一沟槽相同的深度。