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    METHOD OF VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT AND MULTITHREADED PROCESSOR WITH VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT
    11.
    发明申请
    METHOD OF VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT AND MULTITHREADED PROCESSOR WITH VIRTUALIZATION AND OS-LEVEL THERMAL MANAGEMENT 失效
    虚拟化和操作系统级热管理方法和虚拟化和操作级热管理的多处理器

    公开(公告)号：US20090064164A1

    公开(公告)日：2009-03-05

    申请号：US11845243

    申请日：2007-08-27

    申请人： Pradip Bose ,  Chen-Yong Cher ,  Hubertus Franke ,  Hendrik Hamann ,  Eren Kursun ,  Alan J. Weger

    发明人： Pradip Bose ,  Chen-Yong Cher ,  Hubertus Franke ,  Hendrik Hamann ,  Eren Kursun ,  Alan J. Weger

    IPC分类号： G06F9/46

    CPC分类号： G06F1/206 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

    摘要： A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading.

    摘要翻译： 一种在诸如具有同时多线程（SMT）的芯片级多处理器（CMP）的集成电路芯片上管理任务执行的程序产品和方法。 多个芯片操作单元或内核具有用于以单位监测温度的芯片传感器（温度传感器或计数器）。 监视任务执行热任务，特别是热点。 任务执行是平衡的，热的，以最小化热点。 热平衡可以包括同时多线程（SMT）热平衡，芯片级多处理器（CMP）热平衡，推迟识别的热任务的执行，将识别的热任务从当前核心迁移到较冷核心，用户指定的核心跳跃和 SMT硬件线程。

    Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management
    12.
    发明授权
    Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management 失效
    虚拟化和操作系统级热管理方法和具有虚拟化和操作系统级热管理的多线程处理器

    公开(公告)号：US07886172B2

    公开(公告)日：2011-02-08

    申请号：US11845243

    申请日：2007-08-27

    申请人： Pradip Bose ,  Chen-Yong Cher ,  Hubertus Franke ,  Hendrik Hamann ,  Eren Kursun ,  Alan J. Weger

    发明人： Pradip Bose ,  Chen-Yong Cher ,  Hubertus Franke ,  Hendrik Hamann ,  Eren Kursun ,  Alan J. Weger

    IPC分类号： G06F1/32

    CPC分类号： G06F1/206 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

    摘要： A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading.

    摘要翻译： 一种在诸如具有同时多线程（SMT）的芯片级多处理器（CMP）的集成电路芯片上管理任务执行的程序产品和方法。 多个芯片操作单元或内核具有用于以单位监测温度的芯片传感器（温度传感器或计数器）。 监视任务执行热任务，特别是热点。 任务执行是平衡的，热的，以最小化热点。 热平衡可以包括同时多线程（SMT）热平衡，芯片级多处理器（CMP）热平衡，推迟识别的热任务的执行，将识别的热任务从当前核心迁移到较冷核心，用户指定的核心跳跃和 SMT硬件线程。

    Three-dimensional (3D) stacked integrated circuit testing
    14.
    发明授权
    Three-dimensional (3D) stacked integrated circuit testing 有权
    三维（3D）堆叠集成电路测试

    公开(公告)号：US08542030B2

    公开(公告)日：2013-09-24

    申请号：US12942662

    申请日：2010-11-09

    申请人： Chen-Yong Cher ,  Eren Kursun ,  Gary W. Maier ,  Raphael Peter Robertazzi

    发明人： Chen-Yong Cher ,  Eren Kursun ,  Gary W. Maier ,  Raphael Peter Robertazzi

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2817 ,  G01R31/287

    摘要： Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.

    摘要翻译： 三维（3D）集成电路的测试包括通过3D集成电路上的区域和/或层定义第一组部分。 测试还包括将第一强度的应力测试条件应用于第一组零件。 测试还包括通过与第一组部件不同的3D集成电路上的区域和/或层定义第二组部件。 测试进一步包括并将第二强度的应力测试条件应用于第二组零件。 应力测试条件的第二强度大于第一强度，并且由针对第一组和第二组部件确定的灵敏度确定。 根据第一和第二强度应力测试条件的应用结果，确定3D集成电路是否通过了测试。

    Hybrid caching techniques and garbage collection using hybrid caching techniques
    15.
    发明授权
    Hybrid caching techniques and garbage collection using hybrid caching techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US08738859B2

    公开(公告)日：2014-05-27

    申请号：US13613104

    申请日：2012-09-13

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

    Thermal cycling and gradient management in three-dimensional stacked architectures
    16.
    发明授权
    Thermal cycling and gradient management in three-dimensional stacked architectures 有权
    三维堆叠架构中的热循环和梯度管理

    公开(公告)号：US08489217B2

    公开(公告)日：2013-07-16

    申请号：US12984096

    申请日：2011-01-04

    申请人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    发明人： Chen-Yong Cher ,  Wilfried E. Haensch ,  Eren Kursun ,  David R. Motschman

    IPC分类号： G06F19/00

    CPC分类号： G06F1/3234 ,  G06F1/206

    摘要： A mechanism is provided for minimizing reliability problems in a three-dimensional (3D) integrated circuit. A set of sensors are interrogated for current data. A direction of force and a magnitude of the force are determined based on the current data for each sensor in the set of sensors for each of one or more directions between the sensor and at least one neighboring sensor thereby forming a set of forces. Each of the set of forces is used to identify one or more points of stress that are at or above the predetermined force threshold. Responsive to identifying at least one point of stress that is at or above the predetermined force threshold, one or more temperature actuation actions are initiated in order to reduce at least one point of stress in the region where the at least one point of stress is identified.

    摘要翻译： 提供了一种用于最小化三维（3D）集成电路中的可靠性问题的机制。 一组传感器被询问用于当前数据。 基于用于传感器和至少一个相邻传感器之间的一个或多个方向中的每一个的传感器组中的每个传感器的当前数据来确定力的方向和力的大小，从而形成一组力。 所述一组力中的每一个用于识别处于或高于预定力阈值的一个或多个应力点。 响应于识别处于或高于预定力阈值的至少一个应力点，启动一个或多个温度致动动作，以便在识别出至少一个应力点的区域中减少至少一个应力点 。

    Hybrid caching techniques and garbage collection using hybrid caching techniques
    17.
    发明授权
    Hybrid caching techniques and garbage collection using hybrid caching techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US08312219B2

    公开(公告)日：2012-11-13

    申请号：US12395860

    申请日：2009-03-02

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。

    Power Management for Systems On a Chip
    18.
    发明申请
    Power Management for Systems On a Chip 有权
    电源管理系统芯片

    公开(公告)号：US20110191603A1

    公开(公告)日：2011-08-04

    申请号：US12700513

    申请日：2010-02-04

    申请人： Chen-Yong Cher ,  Tejas S. Karkhanis ,  Srinivasan Ramani

    发明人： Chen-Yong Cher ,  Tejas S. Karkhanis ,  Srinivasan Ramani

    IPC分类号： G06F1/00

    CPC分类号： G06F1/00 ,  Y02D10/124

    摘要： A system for controlling a multitasking microprocessor system includes an interconnect, a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink, and a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units.

    摘要翻译： 用于控制多任务微处理器系统的系统包括互连，连接到形成单源单一信宿流网络的互连的多个处理单元，其中所述多个处理单元将数据从单一源传递到 所述单个接收器和连接到所述互连的监视器，用于监视所述多个处理单元中的每一个所消耗的资源的一部分，并且用于根据所述资源的预定预算控制所述多个处理单元以控制数据溢出条件 ，其中所述监视器控制所述多个处理单元的性能和功率模式。

    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION
    19.
    发明申请
    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION 失效
    静态芯片在带有变化的系统中的关闭效率

    公开(公告)号：US20110172984A1

    公开(公告)日：2011-07-14

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06F9/455

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

    Hybrid Caching Techniques and Garbage Collection Using Hybrid Caching Techniques
    20.
    发明申请
    Hybrid Caching Techniques and Garbage Collection Using Hybrid Caching Techniques 有权
    混合缓存技术和使用混合缓存技术的垃圾收集

    公开(公告)号：US20100223429A1

    公开(公告)日：2010-09-02

    申请号：US12395860

    申请日：2009-03-02

    申请人： Chen-Yong Cher ,  Michael K. Gschwind

    发明人： Chen-Yong Cher ,  Michael K. Gschwind

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0848 ,  G06F12/0253 ,  G06F12/0837 ,  G06F12/0875 ,  G06F2212/251 ,  G06F2212/253

    摘要： Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

    摘要翻译： 提供了使用混合缓存技术的混合缓存技术和垃圾收集。 执行对数据对象的特性的度量的确定，该特性指示与数据对象相关联的访问模式。 执行从多个缓存结构中选择一个高速缓存结构，其中基于特性的测量来存储数据对象。 存储数据对象的多个高速缓存结构中的每个单独的缓存结构具有与该个别缓存结构中的每个其他数据对象相似的特征量度。 数据对象存储在所选择的缓存结构中，并且对存储在所选择的高速缓存结构中的数据对象执行至少一个处理操作。