公开(公告)号：US08187975B1

公开(公告)日：2012-05-29

申请号：US12960736

申请日：2010-12-06

Applicant: Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

Inventor： Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

IPC: H01L21/20 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/36

CPC classification number: H01L21/02661 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636

Abstract: A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

Abstract translation: 使用其中半导体结构被接收在适于支持蚀刻工艺和外延生长工艺两者的处理室中的工艺来形成凸起的源极 - 漏极结构。 该半导体结构包括源极区和漏极区，其中源区和漏区各自包括受损的表面层。 控制处理室以设定所需的气氛并设定所需的温度。 在所需的气氛和温度下，处理室的蚀刻过程用于从源极和漏极区域去除损坏的表面层并暴露界面。 在不释放期望的气氛的同时保持期望的温度，处理室的外延生长过程用于从暴露的界面表面生长在源极和漏极区之上的凸起区域。

公开(公告)号：US09768055B2

公开(公告)日：2017-09-19

申请号：US13590836

申请日：2012-08-21

Applicant: Qing Liu ,  Nicolas Loubet ,  Prasanna Khare ,  Shom Ponoth ,  Maud Vinet ,  Bruce Doris

Inventor： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare ,  Shom Ponoth ,  Maud Vinet ,  Bruce Doris

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76232 ,  H01L29/66772 ,  H01L29/78654

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

公开(公告)号：US08828851B2

公开(公告)日：2014-09-09

申请号：US13487583

申请日：2012-06-04

Applicant: Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/336 ,  H01L21/20 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7848

Abstract: An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.

Abstract translation: SOI衬底具有与第二区域隔离的第一区域。 SiGe层沉积在第二区域中的SOI衬底的顶部上。 对衬底进行热氧化处理，其在GeGe层中驱动Ge，以在第二区域和上覆氧化物层中形成SiGeOI结构。 如果SOI衬底在第一区域中暴露，则热氧化工艺进一步产生覆盖第一区域的氧化物层。 去除氧化物层以暴露第一区域中的Si沟道层和第二区域中的SiGe沟道层。 在每个Si沟道层和SiGe沟道层上形成晶体管栅极叠层。 上升的源极和漏极区域由Si沟道层和与晶体管栅极叠层相邻的SiGe沟道层形成。

公开(公告)号：US08796147B2

公开(公告)日：2014-08-05

申请号：US12971054

申请日：2010-12-17

Applicant: Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L21/311 ,  H01L21/302

CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

公开(公告)号：US20130193514A1

公开(公告)日：2013-08-01

申请号：US13487583

申请日：2012-06-04

Applicant: Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/336 ,  H01L21/20 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7848

Abstract: An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.

Abstract translation: SOI衬底具有与第二区域隔离的第一区域。 SiGe层沉积在第二区域中的SOI衬底的顶部上。 对衬底进行热氧化处理，其在GeGe层中驱动Ge，以在第二区域和上覆氧化物层中形成SiGeOI结构。 如果SOI衬底在第一区域中暴露，则热氧化工艺进一步产生覆盖第一区域的氧化物层。 去除氧化物层以暴露第一区域中的Si沟道层和第二区域中的SiGe沟道层。 在每个Si沟道层和SiGe沟道层上形成晶体管栅极叠层。 上升的源极和漏极区域由Si沟道层和与晶体管栅极叠层相邻的SiGe沟道层形成。

公开(公告)号：US08703550B2

公开(公告)日：2014-04-22

申请号：US13525642

申请日：2012-06-18

Applicant: Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract translation: 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。