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    Dual shallow trench isolation liner for preventing electrical shorts
    1.
    发明授权
    Dual shallow trench isolation liner for preventing electrical shorts 有权
    双浅沟槽隔离衬垫，用于防止电气短路

    公开(公告)号：US08703550B2

    公开(公告)日：2014-04-22

    申请号：US13525642

    申请日：2012-06-18

    申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

    摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

    摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

    DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS
    2.
    发明申请
    DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS 有权
    用于防止电气短路的双层防爆隔离衬套

    公开(公告)号：US20130334651A1

    公开(公告)日：2013-12-19

    申请号：US13525642

    申请日：2012-06-18

    申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

    摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

    摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

    ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS
    5.
    发明申请
    ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS 有权
    电子设备，包括具有底部氮化物衬里和上氧化物衬里的浅层分离（STI）区域及相关方法

    公开(公告)号：US20140054698A1

    公开(公告)日：2014-02-27

    申请号：US13590703

    申请日：2012-08-21

    申请人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare

    发明人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

    摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

    摘要翻译： 电子器件可以包括衬底，覆盖衬底的掩埋氧化物（BOX）层，覆盖BOX层的至少一个半导体器件，以及衬底中的至少一个STI区域，并与该至少一个半导体器件相邻。 所述至少一个STI区域限定与所述衬底的侧壁表面，并且可以包括衬在所述侧壁表面的底部部分的氮化物层，在所述底部部分的上方衬着所述侧壁表面的顶部的氧化物层以及所述侧壁表面内的绝缘材料 氮化物和氧化物层。

    HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION
    6.
    发明申请
    HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION 有权
    在一个单一的室中的氢氯酸盐和低温外延，用于提高源水排放

    公开(公告)号：US20120142121A1

    公开(公告)日：2012-06-07

    申请号：US12960736

    申请日：2010-12-06

    申请人： Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

    发明人： Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

    IPC分类号： H01L21/306

    CPC分类号： H01L21/02661 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636

    摘要： A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

    摘要翻译： 使用其中半导体结构被接收在适于支持蚀刻工艺和外延生长工艺两者的处理室中的工艺来形成凸起的源极 - 漏极结构。 该半导体结构包括源极区和漏极区，其中源区和漏区各自包括受损的表面层。 控制处理室以设定所需的气氛并设定所需的温度。 在所需的气氛和温度下，处理室的蚀刻过程用于从源极和漏极区域去除损坏的表面层并暴露界面。 在不释放期望的气氛的同时保持期望的温度，处理室的外延生长过程用于从暴露的界面表面生长在源极和漏极区之上的凸起区域。

    Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods
    8.
    发明授权
    Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods 有权
    电子器件包括具有底部氮化物衬垫和上部氧化物衬垫的浅沟槽隔离（STI）区域及相关方法

    公开(公告)号：US09000555B2

    公开(公告)日：2015-04-07

    申请号：US13590703

    申请日：2012-08-21

    申请人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare

    发明人： Qing Liu ,  Nicolas Loubet ,  Prasanna Khare

    IPC分类号： H01L21/70 ,  H01L21/762

    CPC分类号： H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

    摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

    摘要翻译： 电子器件可以包括衬底，覆盖衬底的掩埋氧化物（BOX）层，覆盖BOX层的至少一个半导体器件，以及衬底中的至少一个STI区域，并与该至少一个半导体器件相邻。 所述至少一个STI区域限定与所述衬底的侧壁表面，并且可以包括衬在所述侧壁表面的底部部分的氮化物层，在所述底部部分的上方衬着所述侧壁表面的顶部的氧化物层以及所述侧壁表面内的绝缘材料 氮化物和氧化物层。

    LAYER FORMATION WITH REDUCED CHANNEL LOSS
    9.
    发明申请
    LAYER FORMATION WITH REDUCED CHANNEL LOSS 有权
    具有减少通道损失的层形成

    公开(公告)号：US20120156847A1

    公开(公告)日：2012-06-21

    申请号：US12971054

    申请日：2010-12-17

    申请人： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

    发明人： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

    IPC分类号： H01L21/336 ,  H01L21/302

    CPC分类号： H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

    摘要： Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

    摘要翻译： 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

    Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication
    10.
    发明授权
    Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication 有权
    在单个腔室中进行盐酸蚀刻和低温外延，用于提高源极 - 漏极制造

    公开(公告)号：US08187975B1

    公开(公告)日：2012-05-29

    申请号：US12960736

    申请日：2010-12-06

    申请人： Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

    发明人： Prasanna Khare ,  Nicolas Loubet ,  Qing Liu

    IPC分类号： H01L21/20 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/36

    CPC分类号： H01L21/02661 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/66636

    摘要： A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions.

    摘要翻译： 使用其中半导体结构被接收在适于支持蚀刻工艺和外延生长工艺两者的处理室中的工艺来形成凸起的源极 - 漏极结构。 该半导体结构包括源极区和漏极区，其中源区和漏区各自包括受损的表面层。 控制处理室以设定所需的气氛并设定所需的温度。 在所需的气氛和温度下，处理室的蚀刻过程用于从源极和漏极区域去除损坏的表面层并暴露界面。 在不释放期望的气氛的同时保持期望的温度，处理室的外延生长过程用于从暴露的界面表面生长在源极和漏极区之上的凸起区域。